Liquid crystal display device and electronic device including the liquid crystal display device

ABSTRACT

In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×10 14 /cm 3 .

TECHNICAL FIELD

An embodiment of the present invention relates to a liquid crystaldisplay device. An embodiment of the present invention relates to anelectronic device including the liquid crystal display device.

BACKGROUND ART

Thin film transistors formed over a flat plate such as a glass substratehave been manufactured using amorphous silicon or polycrystallinesilicon, as typically seen in liquid crystal display devices. Thin filmtransistors manufactured using amorphous silicon have low field effectmobility but can be formed over a large glass substrate. On the otherhand, thin film transistors manufactured using crystalline silicon havehigh field effect mobility, but due to a crystallization step such aslaser annealing, such a transistor is not necessarily suitable for beingformed over a large glass substrate.

In view of the foregoing, attention has been drawn to a technique bywhich a thin film transistor is manufactured using an oxidesemiconductor, and such a transistor is applied to an electronic deviceor an optical device. For example, Patent Document 1 discloses atechnique by which a thin film transistor is manufactured using zincoxide or an In—Ga—Zn—O-based oxide semiconductor as an oxidesemiconductor film, and such a transistor is used as, for example, aswitching element of a liquid crystal display device.

REFERENCE

[Patent Document 1] Japanese Published Patent Application No.2006-165528

DISCLOSURE OF INVENTION

A thin film transistor in which an oxide semiconductor is used for achannel region achieves higher field effect mobility than a thin filmtransistor in which amorphous silicon is used for a channel region. Apixel including such a thin film transistor including an oxidesemiconductor is expected to be applied to a display device such as aliquid crystal display device.

Each pixel included in a liquid crystal display device is provided witha storage capacitor in which a voltage for controlling the orientationof a liquid crystal element is held. Off-state current of a thin filmtransistor is one factor by which the amount of the storage capacitanceis determined. A reduction in off-state current which leads to theextension of a period for holding a voltage in the storage capacitor isimportant for a reduction in power consumption when a still image or thelike is displayed.

Note that in this specification, off-state current is current whichflows between a source and a drain when a thin film transistor is in anoff state (also called a non-conductive state). In the case of ann-channel thin film transistor (for example, with a threshold voltage ofabout 0 V to 2 V), the off-state current means a current which flowsbetween a source and a drain when a negative voltage is applied betweena gate and the source.

Further, as a liquid crystal display device with higher value added,such as a 3D display or a 4 k2 k display, a liquid crystal displaydevice including a pixel in which the area per pixel is expected to besmall and the aperture ratio is improved is needed. It is important toreduce the area of the holding capacitor in order to improve theaperture ratio. Accordingly, the off-state current of a thin filmtransistor needs to be decreased.

In view of the foregoing, it is an object of one embodiment of thepresent invention to provide a liquid crystal display device in which anoff-state current of a thin film transistor using an oxide semiconductorcan be reduced in a pixel.

An embodiment of the present invention is a liquid crystal displaydevice including a plurality of pixels in a display portion andconfigured to perform display in a plurality of frame periods. Each ofthe plurality of frame periods includes a writing period and a holdingperiod. After an image signal is input to each of the plurality ofpixels in the writing period, a transistor included in each of theplurality of pixels is turned off and the image signal is held for atleast 30 seconds in the holding period.

An embodiment of the present invention is a liquid crystal displaydevice including a plurality of pixels in a display portion andconfigured to perform display in a plurality of frame periods. Each ofthe plurality of frame periods includes a writing period and a holdingperiod. After an image signal with a voltage whose polarity is inverteda plurality of times is input to each of the plurality of pixels in thewriting period, a transistor included in each of the plurality of pixelsis turned off and the image signal is held for at least 30 seconds inthe holding period.

In the liquid crystal display device of the embodiment of the presentinvention, a polarity of the voltage of the image signal supplied toeach of the plurality of pixels in the holding period may be a polarityof the voltage supplied at the end of the writing period.

In the liquid crystal display device of the embodiment of the presentinvention, the transistor may include a semiconductor layer including anoxide semiconductor, and the oxide semiconductor may have a carrierconcentration of less than 1×10¹⁴/cm³.

In the liquid crystal display device of the embodiment of the presentinvention, the off-state current per micrometer of channel width of thetransistor may be 1×10⁻¹⁷ A or less.

In a pixel including a thin film transistor using an oxidesemiconductor, the off-state current can be reduced. Therefore, a liquidcrystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained. Further, theaperture ratio can be improved, so that a liquid crystal display deviceincluding a high-definition display portion can be obtained.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1C illustrate a top view and cross-sectional views of aliquid crystal display device.

FIG. 2 is a block diagram of a liquid crystal display device.

FIGS. 3A and 3B illustrate the operation of a liquid crystal displaydevice.

FIGS. 4A and 4B illustrate a top view and a cross-sectional view of aliquid crystal display device.

FIGS. 5A and 5B illustrate a thin film transistor.

FIGS. 6A to 6E illustrate a method manufacturing a thin film transistor.

FIGS. 7A and 7B illustrate a thin film transistor.

FIGS. 8A to 8E illustrate a thin film transistor.

FIGS. 9A and 9B each illustrate a thin film transistor.

FIGS. 10A to 10E illustrate a thin film transistor.

FIGS. 11A to 11E illustrate a thin film transistor.

FIGS. 12A to 12D illustrate a thin film transistor.

FIGS. 13A to 13D illustrate a thin film transistor.

FIG. 14 illustrates a thin film transistor.

FIGS. 15A to 15C illustrate a liquid crystal panel.

FIGS. 16A to 16C illustrate electronic devices.

FIGS. 17A to 17C illustrate electronic devices.

FIG. 18 is a diagram for illustrating Embodiment 13.

FIGS. 19A and 19B are diagrams for illustrating Embodiment 13.

FIGS. 20A and 20B are diagrams for illustrating Embodiment 13.

FIG. 21 is a diagram for illustrating Embodiment 13.

FIG. 22 is a diagram for illustrating Embodiment 14.

FIGS. 23A and 23B are diagrams for illustrating Embodiment 14.

FIGS. 24A and 24B are diagrams for illustrating Embodiment 14.

FIGS. 25A to 25C illustrate a structure of a shift register.

FIG. 26 is a timing chart for illustrating the operation of a shiftregister.

FIG. 27 is a timing chart for illustrating the operation of a shiftregister.

FIG. 28 is a diagram for illustrating a liquid crystal display device ofExample 1.

FIG. 29 is a diagram for illustrating a liquid crystal display device ofExample 1.

FIG. 30 is a diagram for illustrating a liquid crystal display device ofExample 1.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments and examples of the present invention will be described indetail with reference to the drawings. Note that the invention is notlimited to the following description, and it will be easily understoodby those skilled in the art that various changes and modifications canbe made without departing from the spirit and scope of the invention.Therefore, the present invention should not be interpreted as beinglimited to the description of the embodiments and examples below. Notethat in the structure of the invention described below, portions thatare identical or portions having similar functions in different drawingsare denoted by the same reference numerals, and their repetitivedescription will be omitted.

Note that the size, the thickness of a layer, or a region of eachstructure illustrated in drawings in this specification is exaggeratedfor simplicity in some cases. Therefore, embodiments and examples of thepresent invention are not limited to such scales.

Note that the terms such as “first”, “second”, and “third” used in thisspecification are used just to avoid confusion of structural elementsand do not mean limitation of the number of the structural elements.Therefore, for example, description can be made even when “first” isreplaced with “second” or “third”, as appropriate.

Embodiment 1

An example is described below in which a pixel of a liquid crystaldisplay device is formed using a thin film transistor. In thisembodiment, a thin film transistor (hereinafter also referred to as aTFT) included in a pixel of a liquid crystal display device, and anelectrode functioning as a pixel electrode connected to the TFT (simplyalso referred to as a pixel electrode) are described as examples. Notethat a pixel refers to an element group which includes elements providedin each pixel of a display device, for example, an element forcontrolling display in accordance with electric signals, such as a thinfilm transistor, an electrode functioning as a pixel electrode, or awiring. Note that a pixel may include a color filter and the like, andmay correspond to one color component whose brightness can be controlledwith one pixel. Therefore, for example, in the case of a color displaydevice including color components of R, G, and B, a minimum unit of animage includes three pixels of R, G, and B and an image can be obtainedwith a plurality of pixels. Note that an embodiment of the presentinvention is not limited to a color display device and may be amonochrome display device.

Note that “A and B are connected to each other” includes a case where Aand B are electrically connected to each other and a case where A and Bare directly connected to each other. Here, each of A and B correspondsto an object (e.g., a device, an element, a circuit, a wiring, anelectrode, a terminal, a conductive film, a layer, or the like).

First, a top view of a pixel is illustrated in FIG. 1A. Note that FIG.1A illustrates a bottom-gate structure as an example of a structure of aTFT. Note that FIG. 1A illustrates a so-called inverted staggeredstructure in which wiring layers serving as a source electrode and adrain electrode of a TFT are provided on the opposite side of an oxidesemiconductor layer serving as a channel region with respect to a wiringserving as a gate.

A pixel 100 illustrated in FIG. 1A includes a first wiring 101functioning as a scan line, a second wiring 102A functioning as a signalline, an oxide semiconductor layer 103, a capacitor line 104, and apixel electrode 105. In addition, the pixel 100 includes a third wiring102B for electrically connecting the oxide semiconductor layer 103 andthe pixel electrode 105 to each other, in which a thin film transistor106 is formed. The first wiring 101 is also a wiring functioning as agate of the thin film transistor 106. The second wiring 102A is also awiring functioning as one of a source electrode and a drain electrodeand one electrode of a storage capacitor. The third wiring 102B is alsoa wiring functioning as the other of the source electrode and the drainelectrode. The capacitor line 104 is a wiring functioning as the otherelectrode of the storage capacitor.

Note that for simplification of a process, it is preferable that thefirst wiring 101 and the capacitor line 104 are provided in the samelayer and the second wiring 102A and the third wiring 102B are providedin the same layer. Furthermore, the third wiring 102B and the capacitorline 104 are provided so as to partly overlap each other and form thestorage capacitor for a liquid crystal element. Note that the oxidesemiconductor layer 103 included in the thin film transistor 106 isprovided over a wiring diverging from the first wiring 101 with a gateinsulating film (not shown) interposed therebetween.

FIG. 1B illustrates a cross-sectional structure taken along chain lineA1-A2 of FIG. 1A. In the cross-sectional structure illustrated in FIG.1B, the first wiring 101 serving as a gate and the capacitor line 104are provided over a substrate 111 with a base film 112 interposedtherebetween. A gate insulating film 113 is provided so as to cover thefirst wiring 101 and the capacitor line 104. The oxide semiconductorlayer 103 is provided over the gate insulating film 113. The secondwiring 102A and the third wiring 102B are provided over the oxidesemiconductor layer 103. In addition, an oxide insulating layer 114functioning as a passivation film is provided over the oxidesemiconductor layer 103, the second wiring 102A, and the third wiring102B. An opening portion is formed in the oxide insulating layer 114,and in the opening portion, the pixel electrode 105 and the third wiring102B are connected to each other. Furthermore, a capacitor is formed bythe third wiring 102B, the capacitor line 104, and the gate insulatingfilm 113 which serves as a dielectric.

FIG. 1C illustrates a cross-sectional view taken along chain line B1-B2of FIG. 1A and illustrates a structure in which an insulating layer 121is provided between the capacitor line 104 and the second wiring 102A.

In the case where the second wiring 102A is provided over the firstwiring 101 and the capacitor line 104, a parasitic capacitance may begenerated between the first wiring 101 and the second wiring 102A andbetween the capacitor line 104 and the second wiring 102A, depending onthe thickness of the gate insulating film 113. Therefore, by providingthe insulating layer 121 as illustrated in FIG. 1C, a parasiticcapacitance can be reduced and a defect such as malfunction can bereduced.

Note that the pixel illustrated in FIGS. 1A to 1C corresponds to one ofa plurality of pixels 201 arranged in matrix over a substrate 200 asillustrated in FIG. 2. FIG. 2 illustrates a structure in which a pixelportion 202, a scan line driver circuit 203, and a signal line drivercircuit 204 are provided over the substrate 200. Whether the pixels 201are in a selected state or in a non-selected state is determined foreach line in accordance with a scan signal supplied from the firstwiring 101 connected to the scan line driver circuit 203. The pixel 201selected by the scan signal is supplied with a video voltage (alsoreferred to as an image signal, a video signal, or video data) throughthe wiring 102A connected to the signal line driver circuit 204.

Although FIG. 2 illustrates a structure in which the scan line drivercircuit 203 and the signal line driver circuit 204 are provided over thesubstrate 200, a structure may be employed in which one of the scan linedriver circuit 203 and the signal line driver circuit 204 is providedover the substrate 200 and the other is formed over another substrate(e.g., a single crystal silicon substrate) and then connected to thepixel portion 202 by a mounting technique such as a TAB method or a COGmethod. Alternatively, a structure may be employed in which only thepixel portion 202 is provided over the substrate 200 and the scan linedriver circuit 203 and the signal line driver circuit 204 are formedover another substrate and then connected to the pixel portion 202 by amounting technique such as a TAB method or a COG method.

FIG. 2 illustrates an example in which the plurality of pixels 201 isarranged in matrix (in stripe) in the pixel portion 202. Note that thepixels 201 do not necessarily need to be arranged in matrix and may bearranged in a delta pattern or a Bayer pattern, for example. As adisplay method of the pixel portion 202, either a progressive method oran interlace method can be employed. Note that color componentscontrolled in the pixel for color display are not limited to threecolors of R, G, and B (R, G, and B correspond to red, greed, and blue,respectively) and color components of more than three colors may beemployed, for example, R, G, B, and W (W corresponds to white), R, B,and one or more of yellow, cyan, magenta, and the like, or the like.Note that the sizes of display regions may be different betweenrespective dots of color components.

In FIG. 2, the numbers of the first wirings 101 and the second wirings102A correspond to the numbers of the pixels in a column direction and arow direction. Note that the numbers of the first wirings 101 and thesecond wirings 102A may be increased depending on the number ofsub-pixels included in the pixels or the number of the transistors inthe pixels. Alternatively, the pixel 201 may be driven by the firstwiring 101 and the second wiring 102A which are shared with otherpixels.

Note that FIG. 1A illustrates the second wiring 102A of the TFT ashaving a rectangular shape; alternatively, the second wiring 102A may beformed in such a shape as to surround the third wiring 102B(specifically, a U shape or a C shape) so that the area of a region inwhich carriers move can be increased and the amount of current flowingwhen the thin film transistor is turned on (also referred to as anon-state current) can be increased.

Note that in this specification, on-state current is current which flowsbetween a source and a drain when a thin film transistor is in an onstate (also called a conductive state). In the case of an n-channel thinfilm transistor, the on-state current means a current which flowsbetween a source and a drain when a voltage applied between a gate andthe source is higher than a threshold voltage (Vth).

Note that an aperture ratio refers to a ratio of an area of a lighttransmitting region to a unit area. As a region occupied by a memberwhich does not transmit light becomes larger, the aperture ratiodecreases, and as a region occupied by a member which transmits lightbecomes larger, the aperture ratio increases. In a liquid crystaldisplay device, the aperture ratio increases by decreasing the area of awiring or a capacitor line overlapping a pixel electrode and the size ofa thin film transistor.

Note that a thin film transistor is an element having at least threeterminals of a gate, a drain, and a source. The thin film transistor hasa channel region between a drain region and a source region and allows acurrent to flow through the drain region, the channel region, and thesource region. Here, since the source and the drain of the thin filmtransistor may change depending on the structure, the operatingcondition, and the like of the thin film transistor, it is difficult todefine which is a source or a drain. Therefore, a region functioning asa source or a drain is not called the source or the drain in some cases.In such a case, for example, one of the source and the drain may bereferred to as a first terminal and the other may be referred to as asecond terminal. Alternatively, one of the source and the drain may bereferred to as a first electrode and the other may be referred to as asecond electrode. Further alternatively, one of the source and the drainmay be referred to as a first region and the other may be referred to asa second region.

Next, the oxide semiconductor layer 103 will be described.

In this embodiment, from an oxide semiconductor, hydrogen (including anOH bond) is removed such that the concentration of hydrogen in the oxidesemiconductor becomes 5×10¹⁹/cm³ or less, preferably 5×10¹⁸/cm³ or less,more preferably 5×10¹⁷/cm³ or less. Then, a thin film transistor whosechannel region is formed using an oxide semiconductor film having acarrier concentration of less than 1×10¹⁴/cm³, preferably 1×10¹²/cm³ orless is formed. Note that the concentration of hydrogen in the oxidesemiconductor layer is measured by an analysis by secondary ion massspectrometry (SIMS).

When the energy gap of an oxide semiconductor is 2 eV or more,preferably 2.5 eV or more, more preferably 3 eV or more, carriesgenerated by thermal excitation are so few that they can be ignored.Thus, impurities such as hydrogen which form donors are reduced as muchas possible so that the carrier concentration becomes less than1×10¹⁴/cm³, preferably 1×10¹²/cm³ or less. In other words, the carrierconcentration of an oxide semiconductor layer is made as close to zeroas possible.

When an oxide semiconductor which is purified by thoroughly removinghydrogen from the oxide semiconductor as described above is used for achannel formation region of a thin film transistor, the drain current is1×10⁻¹³ A or less at a drain voltage in the rang of from 1 V to 10 V anda gate voltage in the range of from −5 V to −20 V even in the case wherethe channel width is 10 mm.

In the case where a circuit of a display device or the like ismanufactured using a thin film transistor having such an extremely smalloff-state current, there is very little leakage. Therefore, anelectrical signal such as a video signal can be held for a longer periodof time.

Specifically, the off-state current per micrometer of channel width ofthe aforementioned transistor including the oxide semiconductor layerand having a channel width of 10 μm can be as small as 10 aA/μm (1×10⁻¹⁷A/μm) or less, and furthermore, 1 aA/μm (1×10⁻¹⁸ A/μm) or less. When atransistor having an extremely small current in an off state (off-statecurrent) is used as a selection transistor in a pixel, an electricalsignal such as a video signal can be held for a longer period of time.Because the holding time can be extended, for example, a holding periodafter writing of a video signal is set to 10 seconds or longer,preferably 30 seconds or longer, more preferably 1 minute or longer andshorter than 10 minutes. By extending the holding period, writingintervals can be set long and power consumption can be more effectivelyreduced.

On the other hand, in the case of a transistor including, for example,low-temperature polysilicon, design or the like is performed on theassumption that the off-state current is approximately 1×10⁻¹² A/μm.Therefore, in the case of a transistor including an oxide semiconductor,which has a storage capacitance equal to that of the transistorincluding low-temperature polysilicon (approximately 0.1 pF), thevoltage holding period can be approximately 10⁴ times as long as that ofthe transistor including low-temperature polysilicon. Furthermore, inthe case of a transistor including amorphous silicon, the off-statecurrent per micrometer of channel width is 1×10⁻¹³ A/μm or more.Therefore, the voltage holding period of a transistor including ahigh-purity oxide semiconductor can be 10⁴ or more times as long as thatof a transistor using amorphous silicon when these transistors havestorage capacitances which are equal or substantially equal to eachother(approximately 0.1 pF).

For example, in an active matrix display device having a thin filmtransistor including low-temperature polysilicon, due to a leakagecurrent of the thin film transistor, there is a loss of charges whichare held in a pixel; thus, rewriting of a video signal is performedevery 16 milliseconds (at 60 frames/second). On the other hand, in anactive matrix display device having the aforementioned thin filmtransistor including the oxide semiconductor layer, the off-statecurrent of the thin film transistor including the oxide semiconductorlayer is much smaller than that in a thin film transistor includinglow-temperature polysilicon; thus, the holding period for every signalwriting can be made 10000 times longer, which is approximately 160seconds.

Because the holding period can be extended, the frequency of signalwriting can be decreased particularly when a still image is displayed.Therefore, the number of times of signal writing to a pixel can bedecreased, and power consumption can be reduced.

The storage capacitor illustrated in FIGS. 1A to 1C is formed by a pairof electrodes and an insulating layer provided as a dielectric betweenthe pair of electrodes. The storage capacitance is set considering theleakage current of a thin film transistor provided in the pixel portionor the like so that charges can be held for a predetermined period. Thesize of the storage capacitor may be set considering the off-statecurrent of a transistor or the like. In this embodiment, because atransistor including a high-purity oxide semiconductor layer is used asthe transistor 106, it is sufficient to provide a storage capacitorhaving a capacitance which is ⅓ or less, preferably ⅕ or less, of aliquid crystal capacitance in each pixel.

In the case of the aforementioned transistor including the high-purityoxide semiconductor layer, the holding period can be set longer.Therefore, the frequency of signal writing can be drastically decreasedparticularly when a still image is displayed. Accordingly, in the caseof displaying a still image or the like which involves less frequentchanges in display, the number of times of signal writing to a pixel canbe decreased, and thus, power consumption can be reduced.

Note that in still image display, refresh operation may be performed asappropriate considering a holding rate of a voltage applied to a liquidcrystal element during a holding period. For example, refresh operationmay be performed at the timing when a voltage is decreased to apredetermined level with respect to the value of voltage (initial value)shortly after a signal is written to a pixel electrode of a liquidcrystal element. The predetermined level is preferably set to a voltageat which flicker is not sensed with respect to the initial value.Specifically, in the case where a display object is an image, refreshoperation (rewrite) is preferably performed every time the voltagebecomes 1.0%, preferably 0.3%, lower than the initial value. In the casewhere a display object is text, refresh operation (rewrite) ispreferably performed every time the voltage becomes 10%, preferably 3%,lower than the initial value.

During the holding period in still image display, a counter electrode(also referred to as a common electrode) can be put in a floating state.Specifically, a switch may be provided between the counter electrode anda power source for supplying a common potential to the counterelectrode. During the writing period, the switch may be turned on andthe common potential may be supplied to the counter electrode; afterthat, during the holding period, the switch may be turned off and thecounter electrode may be put in a floating state. As the switch, it ispreferable to use the aforementioned transistor including thehigh-purity oxide semiconductor layer. With the use of a TFT includingan oxide semiconductor having an extremely small off-state current asdescribed above, the potential between the pixel electrode and thecounter electrode of a liquid crystal display panel hardly changes, andthe still image display can be maintained while a driver circuit isstopped without causing so-called image burn-in of a liquid crystal.

The specific resistance of a liquid crystal material is 1×10¹² Ω·cm ormore, preferably 1×10¹³ Ω·cm or more, more preferably 1×10¹⁴ Ω·cm ormore. Note that the specific resistance in this specification ismeasured at 20° C. In the case where a liquid crystal display device isformed using the liquid crystal material, the resistivity of a portionserving as a liquid crystal element may be 1×10¹¹ Ω·cm or more,furthermore 1×10¹² Ω·cm or more in some cases because there is apossibility that an impurity may be mixed into a liquid crystal layerfrom an alignment film, a sealant, or the like.

As the specific resistance of a liquid crystal material becomes larger,more charges leaking through the liquid crystal material can be reduced,and a decrease over time in voltage for holding an operation state ofthe liquid crystal element can be suppressed. As a result, the holdingperiod can be extended; therefore, the frequency of signal writing canbe decreased, and power consumption of a display device can be reduced.

FIG. 3A illustrates the relationship between a writing period and aholding period in a frame period. In FIG. 3A, periods 251 and 252 eachcorrespond to a holding period, and periods 261 and 262 each correspondto a writing period.

In FIG. 3A, the polarity of a voltage applied to a liquid crystalelement which is a display element (in the diagram, the polarity isindicated by a plus sign or a minus sign) is inverted in every frameperiod. Accordingly, the electric field applied to the liquid crystalelement is not biased, and the degree of deterioration of the liquidcrystal element can be decreased. In the case of the aforementioned thinfilm transistor including the oxide semiconductor layer, the holdingperiod can be set longer; thus, the number of times of writing to apixel can be drastically decreased. Therefore, in the case of displayinga still image or the like which involves less frequent changes indisplay, power consumption can be reduced.

In addition, FIG. 3B illustrates the relationship in the case of writinga voltage whose polarity is inverted a plurality of times in each of thewriting periods 261 and 262 of FIG. 3A. By writing a voltage whosepolarity is inverted a plurality of times in each of the writing periods261 and 262 as illustrated in FIG. 3B, the degree of deterioration of aliquid crystal element can be further decreased. Note that the polarityof the voltage applied at the end of each of the writing periods 261 and262 is a polarity to be held in the holding period.

Note that the voltage applied to a liquid crystal element in FIGS. 3Aand 3B may be input in accordance with dot inversion driving, sourceline inversion driving, gate line inversion driving, frame inversiondriving, or the like.

Note that in the case where a still image is not displayed and a pixelis formed using a thin film transistor including an oxide semiconductorlayer, a moving image can be displayed without a storage capacitor.FIGS. 4A and 4B illustrate a top view and a cross-sectional view of astructure of a pixel in which a storage capacitor is not formed. Thestructure illustrated in FIGS. 4A and 4B corresponds to a structure inwhich the capacitor line in FIGS. 1A and 1B is omitted. As can also beseen from the top view of FIG. 4A and the cross-sectional view of FIG.4B, with the use of a thin film transistor including an oxidesemiconductor layer, a region occupied by the pixel electrode 105, i.e.,the aperture ratio, can be increased. In addition, as can also be seenfrom the cross-sectional view of FIG. 4B, with the use of a thin filmtransistor including an oxide semiconductor layer, a capacitor line canbe eliminated and a region occupied by the pixel electrode 105 can beenlarged; therefore, the aperture ratio can be increased.

With the structure described above in this embodiment, off-state currentcan be decreased in a pixel having a thin film transistor including anoxide semiconductor. Accordingly, a liquid crystal display devicecapable of extending the period in which a storage capacitor can hold avoltage and reducing power consumption when displaying a still image orthe like can be obtained. Furthermore, by an increase in aperture ratio,a liquid crystal display device having a high-definition display portioncan be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 2

In this embodiment, an example of a thin film transistor which can beapplied to a liquid crystal display device described in thisspecification will be described. A thin film transistor 410 described inthis embodiment can be used as the thin film transistor 106 ofEmbodiment 1.

A thin film transistor of this embodiment and an embodiment of a methodfor manufacturing the thin film transistor are described using FIGS. 5Aand 5B and FIGS. 6A to 6E.

FIG. 5A illustrates an example of a planar structure of the thin filmtransistor, and FIG. 5B illustrates an example of a cross-sectionalstructure thereof. The thin film transistor 410 shown in FIGS. 5A and 5Bis a top-gate thin film transistor.

FIG. 5A is a plan view of the top-gate thin film transistor 410 and FIG.5B is a cross-sectional view along line C1-C2 in FIG. 5A.

The thin film transistor 410 includes, over a substrate 400 having aninsulating surface, an insulating layer 407, an oxide semiconductorlayer 412, a source and drain electrode layers 415 a and 415 b, a gateinsulating layer 402, and a gate electrode layer 411. Wiring layers 414a and 414 b are provided in contact with the source and drain electrodelayers 415 a and 415 b, respectively, to be electrically connectedthereto.

The thin film transistor 410 is described as a single-gate thin filmtransistor; a multi-gate thin film transistor including a plurality ofchannel formation regions can be formed when needed.

A process for manufacturing the thin film transistor 410 over thesubstrate 400 is described below with reference to FIGS. 6A to 6E.

Although there is no particular limitation on a substrate which can beused as the substrate 400 having an insulating surface, it is necessarythat the substrate 400 has at least heat resistance high enough towithstand heat treatment to be performed later.

As the substrate 400, a glass substrate whose strain point is higherthan or equal to 730° C. may be used when the temperature of the heattreatment performed later is high. As a material of the glass substrate,a glass material such as aluminosilicate glass, aluminoborosilicateglass, or barium borosilicate glass is used, for example. Note that bycontaining a larger amount of barium oxide (BaO) than boron oxide, aheat-resistant glass substrate which is of more practical use can beformed. Therefore, it is preferable that a glass substrate containingmore BaO than B₂O₃ be used.

Note that a substrate formed using an insulator such as a ceramicsubstrate, a quartz substrate, or a sapphire substrate may be usedinstead of the above-described glass substrate, as the substrate 400.Alternatively, a crystallized glass substrate or the like may be used.Further alternatively, a plastic substrate or the like may be used.

First, the insulating layer 407 which functions as a base film is formedover the substrate 400 having an insulating surface. It is preferablethat an oxide insulating layer such as a silicon oxide layer, a siliconoxynitride layer, an aluminum oxide layer, or an aluminum oxynitridelayer be used as the insulating layer 407 which is in contact with theoxide semiconductor layer. The insulating layer 407 can be formed by aplasma CVD method, a sputtering method, or the like. It is preferable toform the insulating layer 407 by a sputtering method in order to preventthe insulating layer 407 from containing a large amount of hydrogen.

In this embodiment, a silicon oxide layer is formed as the insulatinglayer 407 by a sputtering method. The substrate 400 is transferred intoa chamber, a sputtering gas containing high-purity oxygen in whichhydrogen and moisture are removed is introduced into the chamber, and atarget is used, so that the silicon oxide layer is deposited to thesubstrate 400 as the insulating layer 407. The substrate 400 may be atroom temperature or may be heated.

For example, a silicon oxide film is formed as follows: quartz(preferably, synthetic quartz) is used as the target; the substratetemperature is 108° C.; the distance between the target and thesubstrate (T-S distance) is 60 mm; the pressure is 0.4 Pa; thehigh-frequency power is 1.5 kW; the atmosphere is oxygen and argon (flowrate ratio of oxygen to argon is 25 sccm:25 sccm=1:1); and an RFsputtering method is used. The thickness of the silicon oxide film is100 nm in this embodiment. A silicon target may be used instead of thequartz (preferably, synthetic quartz) to form the silicon oxide film. Asa sputtering gas, oxygen or a mixed gas of oxygen and argon is used inthis embodiment.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the insulating layer 407. This is in orderto prevent the insulating layer 407 from containing hydrogen, a hydroxylgroup, or moisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the insulatinglayer 407 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the insulating layer 407.

Examples of a sputtering method include an RF sputtering method in whicha high-frequency power source is used as a sputtering power source, a DCsputtering method, and a pulsed DC sputtering method in which a bias isapplied in a pulsed manner. The RF sputtering method is mainly used inthe case where an insulating film is formed, and the DC sputteringmethod is mainly used in the case where a metal film is formed.

There is also a multi-target sputtering apparatus in which a pluralityof targets which are formed of different materials from each other canbe set. With the multi-target sputtering apparatus, films of differentmaterials can be stacked to be formed in the same chamber, or pluralkinds of materials can be deposited by electric discharge at the sametime in the same chamber.

In addition, there is also a sputtering apparatus provided with a magnetsystem inside the chamber and used for a magnetron sputtering method, ora sputtering apparatus used for an ECR sputtering method in which plasmagenerated with the use of microwaves is used without using glowdischarge.

Further, as the deposition method using a sputtering method, there is areactive sputtering method in which a target substance and a sputteringgas component are chemically reacted with each other during depositionto form a thin compound film thereof, or a bias sputtering method inwhich a voltage is also applied to a substrate during deposition.

The insulating layer 407 may have a stacked-layer structure; forexample, a stacked-layer structure in which a nitride insulating layersuch as a silicon nitride layer, a silicon nitride oxide layer, analuminum nitride layer, or an aluminum nitride oxide layer and theabove-described oxide insulating layer are stacked in this order overthe substrate 400 may be used.

For example, a silicon nitride layer is formed between the silicon oxidelayer and the substrate 400 by introducing a sputtering gas containinghigh-purity nitrogen in which hydrogen and moisture are removed andusing a silicon target. In that case, it is preferable to removeresidual moisture from the chamber in the formation of the siliconnitride layer as is the case of the deposition of the silicon oxidelayer.

The substrate may be heated at the time of the film deposition of thesilicon nitride layer.

In the case where the silicon nitride layer and the silicon oxide layerare stacked to form the insulating layer 407, the silicon nitride layerand the silicon oxide layer can be formed in the same chamber with thesame silicon target. For example, first, a sputtering gas containingnitrogen is introduced and a silicon target placed inside the chamber isused to form the silicon nitride layer, and then, the sputtering gas isswitched to a sputtering gas containing oxygen and the same silicontarget is used to form the silicon oxide layer. Since the siliconnitride layer and the silicon oxide layer can be formed in successionwithout exposure to the air, an impurity such as hydrogen or moisturecan be prevented from being adsorbed on a surface of the silicon nitridelayer.

Next, an oxide semiconductor film is formed over the insulating layer407.

In order to prevent the oxide semiconductor film from containingimpurities such as hydrogen, a hydroxyl group, and moisture as much aspossible, it is preferable to preheat the substrate 400 provided withthe insulating layer 407 in a preheating chamber of the sputteringapparatus before the film formation so that an impurity such as hydrogenor moisture adsorbed on the substrate 400 is eliminated, and performexhaustion. As an exhaustion unit provided in the preheating chamber, acryopump is preferable. This preheating step is not necessarilyperformed.

Note that before the oxide semiconductor film is formed by a sputteringmethod, it is preferable to perform reverse sputtering in which an argongas is introduced and plasma is generated so that dust on a surface ofthe insulating layer 407 is removed. The reverse sputtering is a methodby which voltage is applied to a substrate side with a high-frequencypower source in an argon atmosphere to generate plasma in the vicinityof the substrate without applying voltage to a target side, so that asurface is modified. Instead of the argon atmosphere, a nitrogenatmosphere, a helium atmosphere, an oxygen atmosphere, or the like maybe used.

The oxide semiconductor film is formed by the sputtering method. Theoxide semiconductor film is formed using an In—Ga—Zn—O-based oxidesemiconductor film, an In—Sn—Zn—O-based oxide semiconductor film, anIn—Al—Zn—O-based oxide semiconductor film, a Sn—Ga—Zn—O-based oxidesemiconductor film, an Al—Ga—Zn—O-based oxide semiconductor film, aSn—Al—Zn—O-based oxide semiconductor film, an In—Zn—O-based oxidesemiconductor film, a Sn—Zn—O-based oxide semiconductor film, anAl—Zn—O-based oxide semiconductor film, an In—O-based oxidesemiconductor film, a Sn—O-based oxide semiconductor film, or aZn—O-based oxide semiconductor film. In this embodiment, the oxidesemiconductor film is formed by a sputtering method using anIn—Ga—Zn—O-based oxide semiconductor target. Specifically, a targethaving a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 [mol %] (that is,In:Ga:Zn=1:1:0.5 [atom %]) is used. Alternatively, a target having acomposition ratio of In:Ga:Zn=1:1:1 [atom %] or In:Ga:Zn=1:1:2 [atom %]can be used. In this embodiment, the filling rate of the oxidesemiconductor target is equal to or greater than 90% and equal to orless than 100%, preferably equal to or greater than 95% and equal to orless than 99.9%. With use of the oxide semiconductor target having highfilling rate, the deposited oxide semiconductor film has high density.The atmosphere for the sputtering may be an atmosphere of a rare gas(typically, argon), an atmosphere of oxygen, or a mixed atmosphere of arare gas and oxygen. The target may contain SiO₂ at 2 wt % or more and10 wt % or less.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide semiconductor film.

The oxide semiconductor film is formed over the substrate 400 asfollows: the substrate is held in the chamber with pressure reduced,residual moisture in the chamber is removed, a sputtering gas from whichhydrogen and moisture are removed is introduced, and the above-describedtarget is used. In order to remove the residual moisture in the chamber,it is preferable to use an adsorption-type vacuum pump. For example, acryopump, an ion pump, or a titanium sublimation pump is preferablyused. As an exhaustion unit, a turbo molecular pump to which a cold trapis added may be used. In the chamber in which exhaustion is performedwith the use of a cryopump, a hydrogen molecule, a compound including ahydrogen atom such as water (H₂O), a compound including a carbon atom,or the like is exhausted. Accordingly, the concentration of impuritiesincluded in the oxide semiconductor film formed in the chamber can bereduced. The substrate may be heated at the time of the film depositionof the oxide semiconductor film.

As an example of the film deposition condition, the following conditionis employed: the temperature of the substrate is room temperature; thedistance between the substrate and the target is 110 mm; the pressure is0.4 Pa; the direct current (DC) power is 0.5 kW; and the atmosphere isoxygen and argon (the flow rate ratio of oxygen to argon is 15 sccm:30sccm). It is preferable that a pulsed direct current (DC) power sourcebe used because dust can be reduced and the film thickness can be madeuniform. The oxide semiconductor film has a thickness of 2 nm to 200 nm,preferably 5 nm to 30 nm. Note that appropriate thickness of the oxidesemiconductor film varies depending on a material thereof; therefore,the thickness may be determined as appropriate depending on thematerial.

Next, the oxide semiconductor film is processed into the island-shapedoxide semiconductor layer 412 by a first photolithography step (see FIG.6A). A resist mask for forming the island-shaped oxide semiconductorlayer 412 may be formed using an inkjet method. Formation of the resistmask by an inkjet method needs no photomask; thus, manufacturing costcan be reduced.

Note that the etching of the oxide semiconductor film may be dryetching, wet etching, or both dry etching and wet etching.

As an etching gas for the dry etching, a gas containing chlorine(chlorine-based gas such as chlorine (Cl₂), boron chloride (BCl₃),silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄)) is preferablyused.

Alternatively, a gas containing fluorine (fluorine-based gas such ascarbon tetrafluoride (CF₄), sulfur fluoride (SF₆), nitrogen fluoride(NF₃), or trifluoromethane (CHF₃)); hydrogen bromide (HBr); oxygen (O₂);any of these gases to which a rare gas such as helium (He) or argon (Ar)is added; or the like can be used.

As the dry etching method, a parallel-plate RIE (reactive ion etching)method or an ICP (inductively coupled plasma) etching method can beused. In order to etch the layer into a desired shape, the etchingconditions (the amount of electric power applied to a coil-shapedelectrode, the amount of electric power applied to an electrode on asubstrate side, the temperature of the electrode on the substrate side,or the like) are adjusted as appropriate.

As an etchant used for wet etching, a mixed solution of phosphoric acid,acetic acid, and nitric acid, an ammonium hydroxide/hydrogen peroxidemixture (a 31 wt % hydrogen peroxide solution:28 wt % ammoniawater:water=5:2:2), or the like can be used. Alternatively, ITO-07N(produced by KANTO CHEMICAL CO., INC.) may be used.

After the wet etching, the etchant is removed by cleaning together withthe material which is etched off. Waste liquid of the etchant containingthe removed material may be purified and the material contained in thewaste liquid may be reused. The resources can be efficiently used andthe cost can be reduced by collecting and reusing a material such asindium included in the oxide semiconductor from the waste liquid afterthe etching.

The etching conditions (such as an etchant, etching time, ortemperature) are appropriately adjusted depending on a material so thatthe material can be etched into a desired shape.

In this embodiment, the oxide semiconductor film is processed into theisland-shaped oxide semiconductor layer 412 by a wet etching methodusing a solution obtained by mixing phosphoric acid, acetic acid, andnitric acid.

In this embodiment, a first heat treatment is performed on the oxidesemiconductor layer 412. The temperature of the first heat treatment ishigher than or equal to 400° C. and lower than or equal to 750° C., andhigher than or equal to 400° C. and lower than the strain point of thesubstrate 400 when the strain point of the substrate 400 is lower thanor equal to 750° C. In this embodiment, the substrate is put in anelectric furnace which is a kind of heat treatment apparatus and heattreatment is performed on the oxide semiconductor layer at 450° C. for 1hour in a nitrogen atmosphere, and then, the temperature is reduced toroom temperature and water or hydrogen is prevented from entering theoxide semiconductor layer, without exposure to the air; thus, an oxidesemiconductor layer is obtained. The oxide semiconductor layer 412 canbe dehydrated or dehydrogenated by the first heat treatment.

The heat treatment apparatus is not limited to an electric furnace andmay be provided with a device that heats an object to be processed bythermal conduction or thermal radiation from a heater such as aresistance heater or the like. For example, an RTA (rapid thermalannealing) apparatus such as a GRTA (gas rapid thermal annealing)apparatus or an LRTA (lamp rapid thermal annealing) apparatus can beused. The LRTA apparatus is an apparatus for heating an object to beprocessed by radiation of light (an electromagnetic wave) emitted from alamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, acarbon arc lamp, a high pressure sodium lamp, or a high pressure mercurylamp. The GRTA apparatus is an apparatus for heat treatment using ahigh-temperature gas. As the gas, an inert gas which does not react byheat treatment with the object to be processed, like nitrogen or a raregas such as argon, is used.

For example, as the first heat treatment, GRTA may be performed asfollows: the substrate is transferred into an inert gas heated to a hightemperature of 650° C. to 700° C., heated for several minutes, andtransferred and taken out of the inert gas heated to the hightemperature. GRTA enables a high-temperature heat treatment in a shorttime.

In the first heat treatment, it is preferable that water, hydrogen, orthe like be not contained in nitrogen or a rare gas such as helium,neon, or argon. It is preferable that nitrogen or a rare gas such ashelium, neon, or argon which is introduced into the heat treatmentapparatus have a purity of 6N (99.9999%) or more, more preferably 7N(99.99999%) or more (that is, the concentration of impurities be 1 ppmor less, more preferably 0.1 ppm or less).

Further, depending on the conditions of the first heat treatment or thematerial of the oxide semiconductor layer, the oxide semiconductor layer412 might be crystallized to be a microcrystalline film or apolycrystalline film. For example, the oxide semiconductor layer may becrystallized to be a microcrystalline oxide semiconductor film in whichthe degree of crystallization is 90% or more, or 80% or more. Further,depending on the conditions of the first heat treatment or the materialof the oxide semiconductor layer, the oxide semiconductor layer 412 maybe an amorphous oxide semiconductor film which does not containcrystalline components. The oxide semiconductor layer may become anoxide semiconductor film in which a microcrystalline portion (with agrain diameter of 1 nm to 20 nm, typically 2 nm to 4 nm) is mixed in anamorphous oxide semiconductor.

The first heat treatment of the oxide semiconductor layer can also beperformed on the oxide semiconductor film before being processed intothe island-shaped oxide semiconductor layer 412. In that case, thesubstrate is taken out from the heat treatment apparatus after the firstheat treatment, and then a photolithography step is performed thereon.

The example in which the heat treatment for dehydration ordehydrogenation of the oxide semiconductor layer is performed shortlyafter the formation of the oxide semiconductor layer 412 is describedabove. However, the heat treatment for dehydration or dehydrogenationmay be performed after a source electrode and a drain electrode arestacked on the oxide semiconductor layer or after a gate insulatinglayer is formed over a source electrode and a drain electrode as long asit is performed after the deposition of the oxide semiconductor layer.

Next, a conductive film is formed over the insulating layer 407 and theoxide semiconductor layer 412. The conductive film may be formed by asputtering method or a vacuum evaporation method. As a material of theconductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W,an alloy containing any of these elements as a component, an alloy filmcontaining any of these elements in combination, or the like can begiven. Further, one or more materials selected from manganese,magnesium, zirconium, beryllium, and yttrium may be used. Further, theconductive film may have a single-layer structure or a stacked-layerstructure of two or more layers. For example, a single-layer structureof an aluminum film including silicon, a two-layer structure in which atitanium film is stacked over an aluminum film, a three-layer structurein which a titanium film, an aluminum film, and a titanium film arestacked in this order, and the like can be given. Alternatively, a film,an alloy film, or a nitride film which contains aluminum (Al) and one ormore elements selected from titanium (Ti), tantalum (Ta), tungsten (W),molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) may beused. In this embodiment, a titanium film with a thickness of 150 nm isformed as the conductive film by a sputtering method.

Next, a resist mask is formed over the conductive film by a secondphotolithography step. The resist mask may be formed using an inkjetmethod. Formation of the resist mask by an inkjet method needs nophotomask; thus, manufacturing cost can be reduced. After that,selective etching is performed, so that the source and drain electrodelayers 415 a and 415 b are formed, and then, the resist mask is removed(see FIG. 6B). It is preferable that an end portion of each of thesource and drain electrode layers have a tapered shape because coveragewith a gate insulating layer stacked thereover is improved.

Note that each material and etching conditions are adjusted asappropriate such that the oxide semiconductor layer 412 is not removedby the etching of the conductive film and the insulating layer 407 underthe oxide semiconductor layer 412 is not exposed.

In this embodiment, since the Ti film is used as the conductive film andthe In—Ga—Zn—O-based oxide semiconductor is used for the oxidesemiconductor layer 412, an ammonium hydrogen peroxide solution (a mixedsolution of ammonia, water, and a hydrogen peroxide solution) is used asan etchant.

In the second photolithography step, in some cases, part of the oxidesemiconductor layer 412 is etched, whereby an oxide semiconductor layerhaving a groove (a depression portion) may be formed.

Light exposure at the time of the formation of the resist mask in thesecond photolithography step may be performed using ultraviolet light,KrF laser light, or ArF laser light. The channel length L of a thin filmtransistor to be formed is determined by a distance between a lower endof the source electrode layer and a lower end of the drain electrodelayer, which are adjacent to each other over the oxide semiconductorlayer 412. In the case where light exposure is performed for a channellength L of less than 25 nm, the light exposure at the time of theformation of the resist mask in the second photolithography step isperformed using extreme ultraviolet light having an extremely shortwavelength of several nanometers to several tens of nanometers. In thelight exposure by extreme ultraviolet light, the resolution is high andthe focus depth is large. Accordingly, the channel length L of the thinfilm transistor can be made to be 10 nm to 1000 nm, the operation speedof a circuit can be increased, and low power consumption can be achievedby extremely small off-state current.

Next, the gate insulating layer 402 is formed over the insulating layer407, the oxide semiconductor layer 412, and the source and drainelectrode layers 415 a and 415 b (see FIG. 6C).

The gate insulating layer 402 can be formed with a single-layerstructure or a stacked-layer structure using one or more of a siliconoxide layer, a silicon nitride layer, a silicon oxynitride layer, asilicon nitride oxide layer, and an aluminum oxide layer by a plasma CVDmethod, a sputtering method, or the like. In order to prevent the gateinsulating layer 402 from containing a large amount of hydrogen, it ispreferable to form the gate insulating layer 402 by a sputtering method.In the case of forming a silicon oxide film by a sputtering method, asilicon target or a quartz target is used as a target, and oxygen or amixed gas of oxygen and argon is used as a sputtering gas. In thisembodiment, a 100-nm-thick silicon oxide layer is formed as follows: thepressure is 0.4 Pa; the high-frequency power is 1.5 kW; the atmosphereis oxygen and argon (flow rate ratio of oxygen to argon is 25 sccm:25sccm=1:1); and an RF sputtering method is used.

The gate insulating layer 402 can have a structure in which a siliconoxide layer and a silicon nitride layer are stacked in this order overthe substrate. A gate insulating layer having a thickness of 70 nm to400 nm, for example, 100 nm, may be formed in such a manner that asilicon oxide layer (SiO_(x) (x>0)) having a thickness of 5 nm to 300 nmis formed by a sputtering method as a first gate insulating layer andthen a silicon nitride layer (SiN_(y) (y>0)) having a thickness of 50 nmto 200 nm is stacked as a second gate insulating layer over the firstgate insulating layer.

Next, a resist mask is formed by a third photolithography step, andselective etching is performed to remove parts of the gate insulatinglayer 402, so that openings 421 a and 421 b reaching the source anddrain electrode layers 415 a and 415 b are formed (see FIG. 6D).

Next, a conductive film is formed over the gate insulating layer 402 andthe openings 421 a and 421 b. In this embodiment, a titanium film with athickness of 150 nm is formed by a sputtering method. After that, aresist mask is formed over the conductive film by a fourthphotolithography step, and the conductive film is selectively etchedusing the resist mask, so that the gate electrode layer 411 and thewiring layers 414 a and 414 b are formed. Note that the resist mask maybe formed by an inkjet method. Formation of the resist mask by an inkjetmethod needs no photomask; thus, manufacturing cost can be reduced.

The gate electrode layer 411 and the wiring layers 414 a and 414 b caneach be formed to have a single-layer or stacked-layer structure using ametal material such as molybdenum, titanium, chromium, tantalum,tungsten, aluminum, copper, neodymium, or scandium, or an alloy materialwhich contains any of these materials as its main component.

For example, as a two-layer structure of each of the gate electrodelayer 411 and the wiring layers 414 a and 414 b, any of the followingstructures is preferable: a two-layer structure of an aluminum layer anda molybdenum layer stacked thereover, a two-layer structure of a copperlayer and a molybdenum layer stacked thereover, a two-layer structure ofa copper layer and a titanium nitride layer or a tantalum nitride layerstacked thereover, and a two-layer structure of a titanium nitride layerand a molybdenum layer. As a three-layer structure, a stack of atungsten layer or a tungsten nitride layer, a layer of an alloy ofaluminum and silicon or an alloy of aluminum and titanium, and atitanium nitride layer or a titanium layer is preferable. The gateelectrode layer can be formed using a light transmitting conductivefilm. As an example of a material of the light transmitting conductivefilm, a light transmitting conductive oxide can be given.

Next, a second heat treatment (preferably at a temperature of 200° C. to400° C., for example, at a temperature of 250° C. to 350° C.) isperformed in an inert gas atmosphere or an oxygen gas atmosphere. Inthis embodiment, the second heat treatment is performed at 250° C. for 1hour in a nitrogen atmosphere. The second heat treatment may beperformed after a protective insulating layer or a planarizationinsulating layer is formed over the thin film transistor 410.

Furthermore, heat treatment may be performed at a temperature of 100° C.to 200° C. for 1 hour to 30 hours in the air. This heat treatment may beperformed at a fixed heating temperature. Alternatively, the followingchange in the heating temperature may be conducted plural timesrepeatedly: the heating temperature is increased from room temperatureto a temperature of 100° C. to 200° C. and then decreased to roomtemperature. This heat treatment may be performed under a reducedpressure before the formation of the oxide insulating layer. Under thereduced pressure, the heat treatment time can be shortened.

Through the above-described process, the thin film transistor 410including the oxide semiconductor layer 412 in which the concentrationof hydrogen, moisture, hydride, and hydroxide is reduced can be formed(see FIG. 6E). The thin film transistor 410 can be used as the thin filmtransistor 106 described in Embodiment 1.

A protective insulating layer or a planarization insulating layer forplanarization may be provided over the thin film transistor 410. Forexample, the protective insulating layer can be formed with asingle-layer structure or a stacked-layer structure using one or more ofa silicon oxide layer, a silicon nitride layer, a silicon oxynitridelayer, a silicon nitride oxide layer, and an aluminum oxide layer.

The planarization insulating layer can be formed using a heat-resistantorganic material such as polyimide, acrylic, benzocyclobutene,polyamide, or epoxy. Other than such organic materials, it is possibleto use a low-dielectric constant material (a low-k material), asiloxane-based resin, PSG (phosphosilicate glass), BPSG(borophosphosilicate glass), or the like. The planarization insulatinglayer may be formed by stacking a plurality of insulating films formedusing these materials.

Note that the siloxane-based resin corresponds to a resin including aSi—O—Si bond formed using a siloxane-based material as a startingmaterial. The siloxane-based resin may include as a substituent anorganic group (e.g., an alkyl group or an aryl group) or a fluoro group.The organic group may include a fluoro group.

There is no particular limitation on the method for forming theplanarization insulating layer. The planarization insulating layer canbe formed, depending on a material thereof, by a method such as asputtering method, an SOG method, a spin coating method, a dippingmethod, a spray coating method, or a droplet discharge method (e.g., aninkjet method, screen printing, or offset printing), or with the use ofa tool such as a doctor knife, a roll coater, a curtain coater, or aknife coater.

By removing residual moisture in the reaction atmosphere at the time ofthe film deposition of the oxide semiconductor film as described above,the concentration of hydrogen and hydride in the oxide semiconductorfilm can be reduced. Accordingly, the oxide semiconductor film can bestabilized.

By using the thin film transistor, which includes the oxidesemiconductor layer and is manufactured as described above, in each of aplurality of pixels of a display portion of a liquid crystal displaydevice, the leakage current from the pixel can be reduced. Accordingly,a liquid crystal display device capable of extending the period in whicha storage capacitor can hold a voltage and reducing power consumptionwhen displaying a still image or the like can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 3

In this embodiment, another example of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. Note that Embodiment 2 can be referredto for the same portions as and the portions and steps having functionssimilar to those in Embodiment 2, and description thereof is notrepeated. Further, a specific description for the same portions isomitted. A thin film transistor 460 described in this embodiment can beused as the thin film transistor 106 of Embodiment 1.

A thin film transistor of this embodiment and an embodiment of a methodfor manufacturing the thin film transistor are described using FIGS. 7Aand 7B and FIGS. 8A to 8E.

FIG. 7A illustrates an example of a planar structure of the thin filmtransistor, and FIG. 7B illustrates an example of a cross-sectionalstructure thereof. The thin film transistor 460 shown in FIGS. 7A and 7Bis a top-gate thin film transistor.

FIG. 7A is a plan view of the top-gate thin film transistor 460 and FIG.7B is a cross-sectional view along line D1-D2 in FIG. 7A.

The thin film transistor 460 includes over, a substrate 450 having aninsulating surface, an insulating layer 457, a source or drain electrodelayer 465 a (465 a 1 and 465 a 2), an oxide semiconductor layer 462, asource or drain electrode layer 465 b, a wiring layer 468, a gateinsulating layer 452, and a gate electrode layer 461 (461 a and 461 b).The source or drain electrode layer 465 a (465 a 1 and 465 a 2) iselectrically connected to a wiring layer 464 through the wiring layer468. Further, although not shown, the source or drain electrode layer465 b is also electrically connected to the wiring layer in an openingformed in the gate insulating layer 452.

A process for manufacturing the thin film transistor 460 over thesubstrate 450 is described below with reference to FIGS. 8A to 8E.

First, the insulating layer 457 which functions as a base film is formedover the substrate 450 having an insulating surface.

In this embodiment, a silicon oxide layer is formed as the insulatinglayer 457 by a sputtering method. The substrate 450 is transferred intoa chamber, a sputtering gas containing high-purity oxygen in whichhydrogen and moisture are removed is introduced into the chamber, and asilicon target or quartz (preferably, synthetic quartz) is used, so thatthe silicon oxide layer is deposited to the substrate 450 as theinsulating layer 457. As a sputtering gas, oxygen or a mixed gas ofoxygen and argon is used in this embodiment.

For example, a silicon oxide film is formed in this embodiment asfollows: quartz (preferably, synthetic quartz) which has a purity of 6Nis used as the target; the substrate temperature is 108° C.; thedistance between the target and the substrate (T-S distance) is 60 mm;the pressure is 0.4 Pa; the high-frequency power is 1.5 kW; theatmosphere is oxygen and argon (flow rate ratio of oxygen to argon is 25sccm:25 sccm=1:1); and an RF sputtering method is used. The thickness ofthe silicon oxide film is 100 nm in this embodiment. A silicon targetmay be used instead of the quartz (preferably, synthetic quartz) to formthe silicon oxide film.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the insulating layer 457. This is in orderto prevent the insulating layer 457 from containing hydrogen, a hydroxylgroup, or moisture. In the chamber in which exhaustion is performed withthe use of a cryopump, a hydrogen molecule, a compound including ahydrogen atom such as water (H₂O), or the like, for example, isexhausted. Accordingly, the concentration of impurities included in theinsulating layer 457 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less, be used as the sputtering gas for thedeposition of the insulating layer 457.

The insulating layer 457 may have a stacked-layer structure; forexample, a stacked-layer structure in which a nitride insulating layersuch as a silicon nitride layer, a silicon nitride oxide layer, analuminum nitride layer, or an aluminum nitride oxide layer and theabove-described oxide insulating layer are stacked in this order overthe substrate 450 may be used.

For example, a silicon nitride layer is formed between the silicon oxidelayer and the substrate 450 by introducing a sputtering gas containinghigh-purity nitrogen in which hydrogen and moisture are removed andusing a silicon target. In that case, it is also preferable to removeresidual moisture in the chamber in the formation of the silicon nitridelayer as is the case of the deposition of the silicon oxide layer.

Next, a conductive film is formed over the insulating layer 457. As amaterial of the conductive film, an element selected from Al, Cr, Cu,Ta, Ti, Mo, and W, an alloy containing any of these elements as acomponent, an alloy film containing any of these elements incombination, or the like can be given. Further, one or more materialsselected from manganese, magnesium, zirconium, beryllium, and yttriummay be used. Further, the conductive film may have a single-layerstructure or a stacked-layer structure of two or more layers. Forexample, a single-layer structure of an aluminum film including silicon,a two-layer structure in which a titanium film is stacked over analuminum film, a three-layer structure in which a titanium film, analuminum film, and a titanium film are stacked in this order, and thelike can be given. Alternatively, a film, an alloy film, or a nitridefilm which contains aluminum (Al) and one or a plurality of elementsselected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum(Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) may be used. Inthis embodiment, a titanium film with a thickness of 150 nm is formed asthe conductive film by a sputtering method. Next, a resist mask isformed over the conductive film by a first photolithography step, andthe source or drain electrode layers 465 a 1 and 465 a 2 are formed byselective etching, and then, the resist mask is removed (see FIG. 8A).The source or drain electrode layers 465 a 1 and 465 a 2, which areshown as being cut in the cross-sectional view, are one continuous film.It is preferable that an end portion of the each of the source or drainelectrode layers have a tapered shape because coverage with a gateinsulating layer stacked thereover is improved.

Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm isformed. Note that appropriate thickness of the oxide semiconductor filmvaries depending on a material thereof; therefore, the thickness may bedetermined as appropriate depending on the material. In this embodiment,the oxide semiconductor film is formed by a sputtering method with theuse of an In—Ga—Zn—O-based oxide semiconductor target.

The oxide semiconductor film is formed over the substrate 450 asfollows: the substrate is held in the chamber with pressure reduced,residual moisture in the chamber is removed, a sputtering gas from whichhydrogen and moisture are removed is introduced, and a target is used.In order to remove the residual moisture in the chamber, it ispreferable to use an adsorption-type vacuum pump. For example, acryopump, an ion pump, or a titanium sublimation pump is preferablyused. As an exhaustion unit, a turbo molecular pump to which a cold trapis added may be used. In the chamber in which exhaustion is performedwith the use of a cryopump, a hydrogen molecule, a compound including ahydrogen atom such as water (H₂O), a compound including a carbon atom,or the like is exhausted. Accordingly, the concentration of impuritiesincluded in the oxide semiconductor film formed in the chamber can bereduced. The substrate may be heated at the time of the film depositionof the oxide semiconductor film.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide semiconductor film.

As an example of the film deposition condition, the following conditionis employed: the temperature of the substrate is room temperature; thedistance between the substrate and the target is 110 mm; the pressure is0.4 Pa; the direct current (DC) power is 0.5 kW; and the atmosphere isoxygen and argon (the flow rate ratio of oxygen to argon is 15 sccm:30sccm).

Next, the oxide semiconductor film is processed into the island-shapedoxide semiconductor layer 462 by a second photolithography step (seeFIG. 8B). In this embodiment, the oxide semiconductor film is processedinto the island-shaped oxide semiconductor layer 462 by a wet etchingmethod using a solution obtained by mixing phosphoric acid, acetic acid,and nitric acid.

In this embodiment, a first heat treatment is performed on the oxidesemiconductor layer 462. The temperature of the first heat treatment ishigher than or equal to 400° C. and lower than or equal to 750° C., andhigher than or equal to 400° C. and lower than the strain point of thesubstrate 450 when the strain point of the substrate 450 is lower thanor equal to 750° C. In this embodiment, the substrate is put in anelectric furnace which is a kind of heat treatment apparatus and heattreatment is performed on the oxide semiconductor layer at 450° C. for 1hour in a nitrogen atmosphere, and then, the temperature is reduced toroom temperature and water or hydrogen is prevented from entering theoxide semiconductor layer, without exposure to the air; thus, an oxidesemiconductor layer is obtained. The oxide semiconductor layer 462 canbe dehydrated or dehydrogenated by the first heat treatment.

The heat treatment apparatus is not limited to an electric furnace andmay be provided with a device that heats an object to be processed bythermal conduction or thermal radiation from a heater such as aresistance heater or the like. For example, an RTA (rapid thermalannealing) apparatus such as a GRTA (gas rapid thermal annealing)apparatus or an LRTA (lamp rapid thermal annealing) apparatus can beused. For example, as the first heat treatment, GRTA may be performed asfollows: the substrate is transferred into an inert gas heated to a hightemperature of 650° C. to 700° C., heated for several minutes, andtransferred and taken out of the inert gas heated to the hightemperature. GRTA enables a high-temperature heat treatment in a shorttime.

In the first heat treatment, it is preferable that water, hydrogen, orthe like be not contained in nitrogen or a rare gas such as helium,neon, or argon. It is preferable that nitrogen or a rare gas such ashelium, neon, or argon which is introduced into the heat treatmentapparatus have a purity of 6N (99.9999%) or more, more preferably 7N(99.99999%) or more (that is, the concentration of impurities be 1 ppmor less, more preferably 0.1 ppm or less).

Further, depending on the conditions of the first heat treatment or thematerial of the oxide semiconductor layer, the oxide semiconductor layer462 might be crystallized to be a microcrystalline film or apolycrystalline film.

The first heat treatment of the oxide semiconductor layer can also beperformed on the oxide semiconductor film before being processed intothe island-shaped oxide semiconductor layer. In that case, the substrateis taken out from the heat treatment apparatus after the first heattreatment, and then a photolithography step is performed thereon.

The example in which the heat treatment for dehydration ordehydrogenation of the oxide semiconductor layer is performed shortlyafter the formation of the oxide semiconductor layer 462 is describedabove. However, the heat treatment for dehydration or dehydrogenationmay be performed after the source or drain electrode 465 b is stacked onthe oxide semiconductor layer or after the gate insulating layer 452 isformed over the source or drain electrode 465 b as long as it isperformed after the deposition of the oxide semiconductor layer.

Next, a conductive film is formed over the insulating layer 457 and theoxide semiconductor layer 462. After that, a resist mask is formed overthe conductive film by a third photolithography step, the conductivefilm is selectively etched to form the source or drain electrode layer465 b and the wiring layer 468, and then, the resist mask is removed(see FIG. 8C). The source or drain electrode layer 465 b and the wiringlayer 468 may be each formed by a similar material and a similar step tothe material and the step of each of the source or drain electrodelayers 465 a 1 and 465 a 2.

In this embodiment, a 150-nm-thick titanium film is formed as each ofthe source or drain electrode layer 465 b and the wiring layer 468 by asputtering method. In this embodiment, since the source or drainelectrode layers 465 a 1 and 465 a 2 and the source or drain electrodelayer 465 b are titanium films which are the same as each other, etchingselectivity between the source or drain electrode layer 465 b and eachof the source or drain electrode layers 465 a 1 and 465 a 2 cannot beprovided. Therefore, in order to prevent the source or drain electrodelayers 465 a 1 and 465 a 2 from being etched when the source or drainelectrode layer 465 b is etched, the wiring layer 468 is provided overthe source or drain electrode layer 465 a 2 which is not covered withthe oxide semiconductor layer 462. In the case where different materialswhich have high selectivity at the time of etching are used to form thesource or drain electrode layers 465 a 1 and 465 a 2 and the source ordrain electrode layer 465 b, the wiring layer 468 by which the source ordrain electrode layer 465 a 2 is protected at the time of etching is notnecessarily provided.

The oxide semiconductor layer 462 may be partly etched off by theetching of the conductive film. Materials and the etching conditions arecontrolled as appropriate so as not to remove the oxide semiconductorlayer 462 beyond necessity.

In this embodiment, since the Ti film is used as the conductive film andthe In—Ga—Zn—O-based oxide semiconductor is used as the oxidesemiconductor layer 462, an ammonium hydrogen peroxide solution (a mixedsolution of ammonia, water, and a hydrogen peroxide solution) is used asan etchant.

In the second photolithography step, in some cases, part of the oxidesemiconductor layer 462 is etched, whereby an oxide semiconductor layerhaving a groove (a depression portion) may be formed. The resist maskused for forming the source or drain electrode layer 465 b and thewiring layer 468 may be formed by an inkjet method. Formation of theresist mask by an inkjet method needs no photomask; thus, manufacturingcost can be reduced.

Next, the gate insulating layer 452 is formed over the insulating layer457, the oxide semiconductor layer 462, the source or drain electrodelayers 465 a 1 and 465 a 2, and the source or drain electrode layer 465b.

The gate insulating layer 452 can be formed with a single-layerstructure or a stacked-layer structure using one or more of a siliconoxide layer, a silicon nitride layer, a silicon oxynitride layer, asilicon nitride oxide layer, and an aluminum oxide layer by a plasma CVDmethod, a sputtering method, or the like. In order to prevent the gateinsulating layer 452 from containing a large amount of hydrogen, it ispreferable to form the gate insulating layer 452 by a sputtering method.In the case of forming a silicon oxide film by a sputtering method, asilicon target or a quartz target is used as a target, and oxygen or amixed gas of oxygen and argon is used as a sputtering gas.

The gate insulating layer 452 may have a structure in which a siliconoxide layer and a silicon nitride layer are stacked in this order overthe source or drain electrode layers 465 a 1 and 465 a 2 and the sourceor drain electrode layer 465 b. In this embodiment, a 100-nm-thicksilicon oxide layer is formed as follows: the pressure is 0.4 Pa; thehigh-frequency power is 1.5 kW; the atmosphere is oxygen and argon (flowrate ratio of oxygen to argon is 25 sccm:25 sccm=1:1); and an RFsputtering method is used.

Next, a resist mask is formed by a fourth photolithography step, andetching is selectively performed to remove part of the gate insulatinglayer 452, so that an opening 423 reaching the wiring layer 468 isformed (see FIG. 8D). An opening reaching the source or drain electrodelayer 465 b may be formed when the opening 423 is formed, though notshown. In this embodiment, the opening reaching the source or drainelectrode layer 465 b is formed after stacking an interlayer insulatinglayer, and a wiring layer for electrical connection is formed in theopening.

Next, a conductive film is formed over the gate insulating layer 452 andthe opening 423. After that, a fifth photolithography step is performed,so that the gate electrode layer 461 (461 a and 461 b) and the wiringlayer 464 are formed. Note that a resist mask may be formed by an inkjetmethod. Formation of the resist mask by an inkjet method needs nophotomask; thus, manufacturing cost can be reduced.

The gate electrode layer 461 (461 a and 461 b) and the wiring layer 464can each be formed to have a single-layer or stacked-layer structureusing a metal material such as molybdenum, titanium, chromium, tantalum,tungsten, aluminum, copper, neodymium, or scandium, or an alloy materialwhich contains any of these materials as its main component.

In this embodiment, a 150-nm-thick titanium film is formed as each ofthe gate electrode layer 461 (461 a and 461 b) and the wiring layer 464by a sputtering method. Although the gate electrode layer 461 (461 a and461 b) is shown as being divided in FIG. 8E, the gate electrode layer461 (461 a and 461 b) is formed so as to overlap a torus-shaped voidformed by the source or drain electrode layers 465 a 1 and 465 a 2 andthe source or drain electrode layer 465 b as shown in FIG. 7A.

Next, a second heat treatment (preferably at a temperature of 200° C. to400° C., for example, at a temperature of 250° C. to 350° C.) isperformed in an inert gas atmosphere or an oxygen gas atmosphere. Inthis embodiment, the second heat treatment is performed at 250° C. for 1hour in a nitrogen atmosphere. The second heat treatment may beperformed after a protective insulating layer or a planarizationinsulating layer is formed over the thin film transistor 460.

Furthermore, heat treatment may be performed at a temperature of 100° C.to 200° C. for 1 hour to 30 hours in the air. This heat treatment may beperformed at a fixed heating temperature. Alternatively, the followingchange in the heating temperature may be conducted plural timesrepeatedly: the heating temperature is increased from room temperatureto a temperature of 100° C. to 200° C. and then decreased to roomtemperature. This heat treatment may be performed under a reducedpressure before the formation of the oxide insulating layer. Under thereduced pressure, the heat treatment time can be shortened.

Through the above-described process, the thin film transistor 460including the oxide semiconductor layer 462 in which the concentrationof hydrogen, moisture, hydride, and hydroxide is reduced can be formed(see FIG. 8E). The thin film transistor 460 can be used as the thin filmtransistor 106 of Embodiment 1.

A protective insulating layer or a planarization insulating layer forplanarization may be provided over the thin film transistor 460.Although not shown, in this embodiment, an opening reaching the sourceor drain electrode layer 465 b is formed in the gate insulating layer452 and the protective insulating layer and/or the planarizationinsulating layer, and a wiring layer which is electrically connected tothe source or drain electrode layer 465 b is formed in the opening.

By removing residual moisture in the reaction atmosphere at the time ofthe film deposition of the oxide semiconductor film as described above,the concentration of hydrogen and hydride in the oxide semiconductorfilm can be reduced. Accordingly, the oxide semiconductor film can bestabilized.

In a plurality of pixels of a display portion of a liquid crystaldisplay device including the thin film transistor using the oxidesemiconductor layer, off-state current can be reduced. Accordingly, aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained. In thisembodiment, the shape of a channel is circular and the source electrodelayer and the drain electrode layer are formed using different layers,whereby the channel length can be decreased and the channel width can beincreased. In this manner, a thin film transistor having a large channelwidth can be formed even in a relatively small area, which enablesswitching for large current. In addition, although the channel width islarge, the off-state current is extremely small since a purified oxidesemiconductor is used.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 4

In this embodiment, other examples of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. Note that Embodiment 2 can be referredto for the same portions as and the portions and steps having functionssimilar to those in Embodiment 2, and description thereof is notrepeated. Further, a specific description for the same portions isomitted. Thin film transistors 425 and 426 described in this embodimentcan each be used as the thin film transistor 106 of Embodiment 1.

Thin film transistors in this embodiment are described using FIGS. 9Aand 9B.

FIGS. 9A and 9B illustrate examples of a cross-sectional structure of athin film transistor. The thin film transistors 425 and 426 shown inFIGS. 9A and 9B are each a kind of thin film transistor having astructure in which an oxide semiconductor layer is interposed between aconductive layer and a gate electrode layer.

In FIGS. 9A and 9B, a silicon substrate 420 is used, and each of thethin film transistors 425 and 426 is provided over an insulating layer422 provided over the silicon substrate 420.

In FIG. 9A, a conductive layer 427 is provided between the insulatinglayer 422 provided over the silicon substrate 420 and an insulatinglayer 407 so as to overlap at least an oxide semiconductor layer 412entirely.

FIG. 9B is an example in which a conductive layer between the insulatinglayer 422 and the insulating layer 407 is processed by etching to be aconductive layer 424 and overlaps at least a portion including a channelregion of the oxide semiconductor layer 412.

The conductive layers 427 and 424 each are formed by a metal materialwhich is resistant to the temperature of a heat treatment performedlater. An element selected from titanium (Ti), tantalum (Ta), tungsten(W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc),an alloy including any of the above elements as its component, an alloyfilm including a combination of any of these elements, a nitrideincluding any of the above elements as its component, or the like can beused. A single-layer structure or a stacked-layer structure may be used;for example, a single layer of a tungsten layer, a stacked-layerstructure of a tungsten nitride layer and a tungsten layer, or the likecan be used.

The potential of each of the conductive layers 427 and 424 may be equalto or different from the potential of the gate electrode layer 411 ofeach of the thin film transistors 425 and 426, and each of theconductive layers 427 and 424 may function as a second gate electrodelayer. The potentials of the conductive layers 427 and 424 may each be afixed potential such as GND or 0 V.

Electrical characteristics of the thin film transistors 425 and 426 canbe controlled by the conductive layers 427 and 424.

This embodiment can be implemented in appropriate combination with anyof other embodiments.

Embodiment 5

In this embodiment, an example of a thin film transistor which can beapplied to a liquid crystal display device disclosed in thisspecification will be described.

A thin film transistor of this embodiment and an embodiment of a methodfor manufacturing the thin film transistor are described using FIGS. 10Ato 10E.

FIGS. 10A to 10E illustrate an example of a cross-sectional structure ofa thin film transistor. A thin film transistor 390 shown in FIGS. 10A to10E is a kind of bottom-gate structure and is also referred to as aninverted staggered thin film transistor.

Although the thin film transistor 390 is described using a single-gatethin film transistor, a multi-gate thin film transistor including aplurality of channel formation regions can be formed as necessary.

Hereinafter, a process for manufacturing the thin film transistor 390over a substrate 394 is described using FIGS. 10A to 10E.

First, a conductive film is formed over the substrate 394 having aninsulating surface, and then, a first photolithography step isperformed, so that a gate electrode layer 391 is formed. It ispreferable that an end portion of the gate electrode layer have atapered shape because coverage with a gate insulating layer stackedthereover is improved. Note that a resist mask may be formed by aninkjet method. Formation of the resist mask by an inkjet method needs nophotomask; thus, manufacturing cost can be reduced.

Although there is no particular limitation on a substrate which can beused as the substrate 394 having an insulating surface, it is necessarythat the substrate 394 has at least heat resistance high enough towithstand heat treatment to be performed later.

For example, in the case where a glass substrate is used as thesubstrate 394, if the temperature of the heat treatment to be performedlater is high, it is preferable to use a glass substrate whose strainpoint is 730° C. or higher. As a material of the glass substrate, aglass material such as aluminosilicate glass, aluminoborosilicate glass,or barium borosilicate glass is used, for example. Note that bycontaining a larger amount of barium oxide (BaO) than boron oxide, aheat-resistant glass substrate which is of more practical use can beformed. Therefore, it is preferable that a glass substrate containingmore BaO than B₂O₃ be used.

Note that a substrate formed using an insulator such as a ceramicsubstrate, a quartz substrate, or a sapphire substrate may be usedinstead of the above-described glass substrate, as the substrate 394.Alternatively, a crystallized glass substrate or the like may be used.Further alternatively, a plastic substrate or the like may be used.

An insulating film which functions as a base film may be providedbetween the substrate 394 and the gate electrode layer 391. The basefilm has a function of preventing diffusion of an impurity element fromthe substrate 394, and can be formed with a single-layer structure or astacked-layer structure using one or more of a silicon nitride film, asilicon oxide film, a silicon nitride oxide film, and a siliconoxynitride film.

The gate electrode layer 391 can be formed to have a single-layer orstacked-layer structure using a metal material such as molybdenum,titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, orscandium, or an alloy material which contains any of these materials asits main component.

For example, as a two-layer structure of the gate electrode layer 391,any of the following structures is preferable: a two-layer structure ofan aluminum layer and a molybdenum layer stacked thereover, a two-layerstructure of a copper layer and a molybdenum layer stacked thereover, atwo-layer structure of a copper layer and a titanium nitride layer or atantalum nitride layer stacked thereover, a two-layer structure of atitanium nitride layer and a molybdenum layer, and a two-layer structureof a tungsten nitride layer and a tungsten layer stacked thereover. As athree-layer structure, a stack of a tungsten layer or a tungsten nitridelayer, a layer of an alloy of aluminum and silicon or an alloy ofaluminum and titanium, and a titanium nitride layer or a titanium layeris preferable. The gate electrode layer can be formed using a lighttransmitting conductive film. As an example of a material of the lighttransmitting conductive film, a light transmitting conductive oxide canbe given.

Next, a gate insulating layer 397 is formed over the gate electrodelayer 391.

The gate insulating layer 397 can be formed with a single-layerstructure or a stacked-layer structure using one or more of a siliconoxide layer, a silicon nitride layer, a silicon oxynitride layer, asilicon nitride oxide layer, and an aluminum oxide layer by a plasma CVDmethod, a sputtering method, or the like. In order to prevent the gateinsulating layer 397 from containing a large amount of hydrogen, it ispreferable to form the gate insulating layer 397 by a sputtering method.In the case of forming a silicon oxide film by a sputtering method, asilicon target or a quartz target is used as a target, and oxygen or amixed gas of oxygen and argon is used as a sputtering gas.

The gate insulating layer 397 can have a structure in which a siliconnitride layer and a silicon oxide layer are stacked in this order overthe gate electrode layer 391. For example, a 100-nm-thick gateinsulating layer is formed in such a manner that a silicon nitride layer(SiN_(y) (y>0)) having a thickness of 50 nm to 200 nm is formed by asputtering method as a first gate insulating layer and then a siliconoxide layer (SiO_(x) (x>0)) having a thickness of 5 nm to 300 nm isstacked as a second gate insulating layer over the first gate insulatinglayer.

In order to prevent the gate insulating layer 397 and an oxidesemiconductor film 393 film from containing hydrogen, a hydroxyl group,and moisture as much as possible, it is preferable to preheat thesubstrate 394 provided with the gate electrode layer 391 or thesubstrate 394 provided with the gate electrode layer 391 and the gateinsulating layer 397 in a preheating chamber of a sputtering apparatusbefore the film formation so that an impurity such as hydrogen ormoisture adsorbed on the substrate 394 is eliminated, and performexhaustion. The temperature of the preheating be higher than or equal to100° C. and lower than or equal to 400° C., preferably higher than orequal to 150° C. and lower than or equal to 300° C. As an exhaustionunit provided in the preheating chamber, a cryopump is preferable. Thispreheating step is not necessarily performed. This preheating step maybe performed in a similar manner on the substrate 394 provided withcomponents up to and including a source electrode layer 395 a and adrain electrode layer 395 b shown in FIG. 10C before an oxide insulatinglayer 396 is formed.

Next, over the gate insulating layer 397, the oxide semiconductor film393 is formed to a thickness of 2 nm to 200 nm, preferably 5 nm to 30 nmby a sputtering method (see FIG. 10A). Note that appropriate thicknessof the oxide semiconductor film varies depending on a material thereof;therefore, the thickness may be determined as appropriate depending onthe material.

Note that before the oxide semiconductor film 393 is formed by asputtering method, it is preferable to perform reverse sputtering inwhich an argon gas is introduced and plasma is generated so that dust ona surface of the gate insulating layer 397 is removed. The reversesputtering is a method by which voltage is applied to a substrate sidewith an RF power source in an argon atmosphere to generate plasma in thevicinity of the substrate without applying voltage to a target side, sothat a surface is modified. Instead of the argon atmosphere, a nitrogenatmosphere, a helium atmosphere, an oxygen atmosphere, or the like maybe used.

The oxide semiconductor film 393 is formed using an In—Ga—Zn—O-basedoxide semiconductor film, an In—Sn—Zn—O-based oxide semiconductor film,an In—Al—Zn—O-based oxide semiconductor film, a Sn—Ga—Zn—O-based oxidesemiconductor film, an Al—Ga—Zn—O-based oxide semiconductor film, aSn—Al—Zn—O-based oxide semiconductor film, an In—Zn—O-based oxidesemiconductor film, a Sn—Zn—O-based oxide semiconductor film, anAl—Zn—O-based oxide semiconductor film, an In—O-based oxidesemiconductor film, a Sn—O-based oxide semiconductor film, or aZn—O-based oxide semiconductor film. In this embodiment, the oxidesemiconductor film 393 is formed by a sputtering method using anIn—Ga—Zn—O-based oxide semiconductor target. Specifically, a targethaving a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 [mol %] (that is,In:Ga:Zn=1:1:0.5 [atom %]) is used. Alternatively, a target having acomposition ratio of In:Ga:Zn=1:1:1 [atom %] or In:Ga:Zn=1:1:2 [atom %]can be used. In this embodiment, the filling rate of the oxidesemiconductor target is equal to or greater than 90% and equal to orless than 100%, preferably equal to or greater than 95% and equal to orless than 99.9%. With use of the oxide semiconductor target having highfilling rate, the deposited oxide semiconductor film has high density.The oxide semiconductor film 393 can be formed by a sputtering method inan atmosphere of a rare gas (typically, argon), an atmosphere of oxygen,or a mixed atmosphere of a rare gas and oxygen. The target may containSiO₂ at 2 wt % or more and 10 wt % or less.

The oxide semiconductor film 393 is formed over the substrate 394 asfollows: the substrate is held in the chamber with pressure reduced, andthe substrate is heated to room temperature or a temperature lower than400° C.; and residual moisture in the chamber is removed, a sputteringgas from which hydrogen and moisture are removed is introduced, and theabove-described target is used. In order to remove residual moisturefrom the chamber, an adsorption-type vacuum pump is preferably used. Forexample, a cryopump, an ion pump, or a titanium sublimation pump ispreferably used. As an exhaustion unit, a turbo molecular pump to whicha cold trap is added may be used. In the chamber in which exhaustion isperformed with the use of a cryopump, a hydrogen molecule, a compoundincluding a hydrogen atom such as water (H₂O), a compound including acarbon atom, or the like, for example, is exhausted. Accordingly, theconcentration of impurities included in the oxide semiconductor filmformed in the chamber can be reduced. By performing deposition bysputtering while removing residual moisture in the chamber using acryopump pump, the substrate temperature during the formation of theoxide semiconductor film 393 can be set higher than or equal to roomtemperature and lower than 400° C.

As an example of the film deposition condition, the following conditionis employed: the distance between the substrate and the target is 100mm; the pressure is 0.6 Pa; the direct current (DC) power is 0.5 kW; andthe atmosphere is oxygen (the proportion of oxygen flow is 100%). It ispreferable that a pulsed direct current (DC) power source be usedbecause dust can be reduced and the film thickness can be made uniform.

Examples of a sputtering method include an RF sputtering method in whicha high-frequency power source is used as a sputtering power source, a DCsputtering method, and a pulsed DC sputtering method in which a bias isapplied in a pulsed manner. The RF sputtering method is mainly used inthe case where an insulating film is formed, and the DC sputteringmethod is mainly used in the case where a metal film is formed.

There is also a multi-target sputtering apparatus in which a pluralityof targets which are formed of different materials from each other canbe set. With the multi-target sputtering apparatus, films of differentmaterials can be stacked to be formed in the same chamber, or pluralkinds of materials can be deposited by electric discharge at the sametime in the same chamber.

In addition, there is also a sputtering apparatus provided with a magnetsystem inside the chamber and used for a magnetron sputtering method, ora sputtering apparatus used for an ECR sputtering method in which plasmagenerated with the use of microwaves is used without using glowdischarge.

Further, as the deposition method using a sputtering method, there is areactive sputtering method in which a target substance and a sputteringgas component are chemically reacted with each other during depositionto form a thin compound film thereof, or a bias sputtering method inwhich a voltage is also applied to a substrate during deposition.

Next, the oxide semiconductor film is processed into an island-shapedoxide semiconductor layer 399 by a second photolithography step (seeFIG. 10B). A resist mask for forming the island-shaped oxidesemiconductor layer 399 may be formed using an inkjet method. Formationof the resist mask by an inkjet method needs no photomask; thus,manufacturing cost can be reduced.

In the case where a contact hole is formed in the gate insulating layer397, a step thereof can be performed at the time of the formation of theoxide semiconductor layer 399.

Note that the etching of the oxide semiconductor film 393 may be dryetching, wet etching, or both dry etching and wet etching.

As an etching gas for the dry etching, a gas containing chlorine(chlorine-based gas such as chlorine (Cl₂), boron chloride (BCl₃),silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄)) is preferablyused.

Alternatively, a gas containing fluorine (fluorine-based gas such ascarbon tetrafluoride (CF₄), sulfur fluoride (SF₆), nitrogen fluoride(NF₃), or trifluoromethane (CHF₃)); hydrogen bromide (HBr); oxygen (O₂);any of these gases to which a rare gas such as helium (He) or argon (Ar)is added; or the like can be used.

As the dry etching method, a parallel-plate RIE (reactive ion etching)method or an ICP (inductively coupled plasma) etching method can beused. In order to etch the layer into a desired shape, the etchingconditions (the amount of electric power applied to a coil-shapedelectrode, the amount of electric power applied to an electrode on asubstrate side, the temperature of the electrode on the substrate side,or the like) are adjusted as appropriate.

As an etchant used for wet etching, a mixed solution of phosphoric acid,acetic acid, and nitric acid, an ammonium hydroxide/hydrogen peroxidemixture (a 31 wt % hydrogen peroxide solution:28 wt % ammoniawater:water=5:2:2), or the like can be used. Alternatively, ITO-07N(produced by KANTO CHEMICAL CO., INC.) may be used.

After the wet etching, the etchant is removed by cleaning together withthe material which is etched off. Waste liquid of the etchant containingthe removed material may be purified and the material contained in thewaste liquid may be reused. The resources can be efficiently used andthe cost can be reduced by collecting and reusing a material such asindium included in the oxide semiconductor from the waste liquid afterthe etching.

The etching conditions (such as an etchant, etching time, ortemperature) are appropriately adjusted depending on a material so thatthe material can be etched into a desired shape.

Note that in that case, before a conductive film is formed in thefollowing step, it is preferable to perform reverse sputtering to removea resist residue or the like from a surface of the oxide semiconductorlayer 399 and the gate insulating layer 397.

Next, a conductive film is formed over the gate insulating layer 397 andthe oxide semiconductor layer 399. The conductive film may be formed bya sputtering method or a vacuum evaporation method. As a material of theconductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W,an alloy containing any of these elements as a component, an alloy filmcontaining any of these elements in combination, or the like can begiven. Further, one or more materials selected from manganese,magnesium, zirconium, beryllium, and yttrium may be used. Further, theconductive film may have a single-layer structure or a stacked-layerstructure of two or more layers. For example, a single-layer structureof an aluminum film including silicon, a two-layer structure in which atitanium film is stacked over an aluminum film, a three-layer structurein which a titanium film, an aluminum film, and a titanium film arestacked in this order, and the like can be given. Alternatively, a film,an alloy film, or a nitride film which contains aluminum (Al) and one ormore elements selected from titanium (Ti), tantalum (Ta), tungsten (W),molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) may beused.

A resist mask is formed over the conductive film by a thirdphotolithography step, and the source electrode layer 395 a and thedrain electrode layer 395 b are formed by selective etching, and then,the resist mask is removed (see FIG. 10C).

Light exposure at the time of the formation of the resist mask in thethird photolithography step is performed using ultraviolet light, KrFlaser light, or ArF laser light. The channel length L of a thin filmtransistor to be formed is determined by a distance between a lower endof the source electrode layer and a lower end of the drain electrodelayer, which are adjacent to each other over the oxide semiconductorlayer 399. In the case where light exposure is performed for a channellength L of less than 25 nm, the light exposure at the time of theformation of the resist mask in the third photolithography step may beperformed using extreme ultraviolet light having an extremely shortwavelength of several nanometers to several tens of nanometers. In thelight exposure by extreme ultraviolet light, the resolution is high andthe focus depth is large. Accordingly, the channel length L of the thinfilm transistor can be made to be 10 nm to 1000 nm, the operation speedof a circuit can be increased, and low power consumption can be achievedby extremely small off-state current.

Note that each material and etching conditions are adjusted asappropriate such that the oxide semiconductor layer 399 is not removedby the etching of the conductive film.

In this embodiment, since a Ti film is used as the conductive film andthe In—Ga—Zn—O-based oxide semiconductor is used for the oxidesemiconductor layer 399, an ammonium hydrogen peroxide solution (a mixedsolution of ammonia, water, and a hydrogen peroxide solution) is used asan etchant.

In the third photolithography step, in some cases, part of the oxidesemiconductor layer 399 is etched, whereby an oxide semiconductor layerhaving a groove (a depression portion) may be formed. The resist maskused for forming the source electrode layer 395 a and the drainelectrode layer 395 b may be formed by an inkjet method. Formation ofthe resist mask by an inkjet method needs no photomask; thus,manufacturing cost can be reduced.

In order to reduce the number of photomasks and steps in thephotolithography step, etching may be performed with the use of a resistmask formed using a multi-tone mask which is a light-exposure maskthrough which light is transmitted so as to have a plurality ofintensities. Since a resist mask formed using a multi-tone mask has aplurality of thicknesses and can be further changed in shape byperforming etching, the resist mask can be used in a plurality ofetching steps to provide different patterns. Therefore, a resist maskcorresponding to at least two kinds of different patterns can be formedby using one multi-tone mask. Thus, the number of light-exposure maskscan be reduced and the number of corresponding photolithography stepscan also be reduced, whereby simplification of the manufacturing processcan be realized.

After the removal of the resist mask, plasma treatment using a gas suchas N₂O, N₂, or Ar may be performed to remove water or the like adsorbedon a surface of the oxide semiconductor layer 399 which is exposed.Plasma treatment may be performed using a mixed gas of oxygen and argon.

Next, the oxide insulating layer 396 is formed as an oxide insulatinglayer which functions as a protective insulating layer which is incontact with part of the oxide semiconductor layer (see FIG. 10D). Inthe case where the plasma treatment is performed, the oxide insulatinglayer 396 may be formed without exposure of the oxide semiconductorlayer 399 to the air successively after the plasma treatment. In thisembodiment, the oxide semiconductor layer 399 is in contact with theoxide insulating layer 396 in a region where the oxide semiconductorlayer 399 overlaps neither the source electrode layer 395 a nor thedrain electrode layer 395 b.

In this embodiment, as the oxide insulating layer 396, a silicon oxidelayer including a defect is formed as follows: the substrate 394 overwhich the island-shaped oxide semiconductor layer 399, the sourceelectrode layer 395 a, and the drain electrode layer 395 b are formed isheated at room temperature to a temperature lower than 100° C.; asputtering gas containing high-purity oxygen from which hydrogen andmoisture are removed is introduced; and a silicon semiconductor targetis used.

For example, the silicon oxide film is formed as follows: a silicontarget doped with boron (with a resistivity of 0.01 Ω·cm) and which hasa purity of 6N is used; the distance between the target and thesubstrate (T-S distance) is 89 mm; the pressure is 0.4 Pa; the directcurrent (DC) power source is 6 kW; the atmosphere is oxygen (theproportion of oxygen flow is 100%); and a pulsed DC sputtering method isused. The thickness of the silicon oxide film is 300 nm in thisembodiment. Quartz (preferably, synthetic quartz) may be used instead ofthe silicon target to form the silicon oxide film.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide insulating layer 396. This is inorder to prevent the oxide semiconductor layer 399 and the oxideinsulating layer 396 from containing hydrogen, a hydroxyl group, ormoisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxideinsulating layer 396 formed in the chamber can be reduced.

As the oxide insulating layer 396, instead of the silicon oxide layer, asilicon oxynitride layer, an aluminum oxide layer, an aluminumoxynitride layer, or the like can be used.

Further, after the formation of the oxide insulating layer 396, heattreatment at 100° C. to 400° C. may be performed in a state where theoxide insulating layer 396 is in contact with the oxide semiconductorlayer 399. Since the oxide insulating layer 396 in this embodimentincludes many defects, an impurity such as hydrogen, moisture, ahydroxyl group, or hydride included in the oxide semiconductor layer 399is diffused into the oxide insulating layer 396 by this heat treatment,so that the impurity included in the oxide semiconductor layer 399 canfurther be reduced.

Through the above-described process, the thin film transistor 390including an oxide semiconductor layer 392 in which the concentration ofhydrogen, moisture, a hydroxyl group, or hydride is reduced can beformed (see FIG. 10E).

By removing residual moisture in the reaction atmosphere at the time ofthe film deposition of the oxide semiconductor film as described above,the concentration of hydrogen and hydride in the oxide semiconductorfilm can be reduced. Accordingly, the oxide semiconductor film can bestabilized.

A protective insulating layer may be provided over the oxide insulatinglayer. In this embodiment, a protective insulating layer 398 is formedover the oxide insulating layer 396. As the protective insulating layer398, a silicon nitride film, a silicon nitride oxide film, an aluminumnitride film, or an aluminum nitride oxide film, or the like can beused.

As the protective insulating layer 398, a silicon nitride film is formedby heating the substrate 394, over which layers up to and including theoxide insulating layer 396 are formed, to a temperature of 100° C. to400° C., introducing a sputtering gas containing high-purity nitrogenfrom which hydrogen and moisture are removed, and using a target ofsilicon semiconductor. In that case, it is also preferable that residualmoisture be removed from the treatment chamber in the formation of theprotective insulating layer 398 as is the case of the oxide insulatinglayer 396.

In the case where the protective insulating layer 398 is formed, thesubstrate 394 is heated to a temperature of 100° C. to 400° C. at thetime of the formation of the protective insulating layer 398, wherebyhydrogen or moisture included in the oxide semiconductor layer can bediffused into the oxide insulating layer. In such a case, heat treatmentafter the formation of the oxide insulating layer 396 is not necessarilyperformed.

In the case where the silicon oxide layer is formed as the oxideinsulating layer 396 and the silicon nitride layer is stacked as theprotective insulating layer 398, the silicon oxide layer and the siliconnitride layer can be formed in the same chamber using a common silicontarget. First, a sputtering gas containing oxygen is introduced and asilicon target placed inside the chamber is used, so that a siliconoxide layer is formed; and then, the sputtering gas is switched to asputtering gas containing nitrogen and the same silicon target is used,so that a silicon nitride layer is formed. Since the silicon oxide layerand the silicon nitride layer can be formed in succession withoutexposure to the air, an impurity such as hydrogen or moisture can beprevented from being adsorbed on a surface of the silicon oxide layer.In that case, after the silicon oxide layer is formed as the oxideinsulating layer 396 and the silicon nitride layer is stacked as theprotective insulating layer 398, heat treatment (at a temperature of100° C. to 400° C.) for diffusing hydrogen or moisture included in theoxide semiconductor layer into the oxide insulating layer may beperformed.

After the formation of the protective insulating layer, heat treatmentmay be performed at a temperature of 100° C. to 200° C. in the air for 1hour to 30 hours. This heat treatment may be performed at a fixedheating temperature. Alternatively, the following change in the heatingtemperature may be conducted plural times repeatedly: the heatingtemperature is increased from room temperature to a temperature of 100°C. to 200° C. and then decreased to room temperature. Further, this heattreatment may be performed under a reduced pressure before the formationof the oxide insulating layer. Under the reduced pressure, the heattreatment time can be shortened. With this heat treatment, a thin filmtransistor which is normally off (which has a positive threshold voltagein the case of an n-channel transistor) can be obtained. Therefore,reliability of the liquid crystal display device can be improved.

Further, by removing residual moisture in the reaction atmosphere at thetime of the formation of the oxide semiconductor layer, in which achannel formation region is to be formed, over the gate insulatinglayer, the concentration of hydrogen or hydride in the oxidesemiconductor layer can be reduced.

The above-described process can be used for manufacturing a backplane (asubstrate over which a thin film transistor is formed) of a liquidcrystal display panel, an electroluminescent display panel, a displaydevice using electronic ink, or the like. Since the above-describedprocess is performed at a temperature of 400° C. or lower, the processcan be applied to a manufacturing process using a glass substrate havinga side longer than one meter and a thickness of one millimeter or less.Further, since the whole process can be performed at a treatmenttemperature of 400° C. or lower, a display panel can be manufacturedwithout consuming too much energy.

In a plurality of pixels of a display portion of a liquid crystaldisplay device including the thin film transistor using the oxidesemiconductor layer, off-state current can be reduced. Accordingly, aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 6

In this embodiment, another example of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. A thin film transistor 310 described inthis embodiment can be used as the thin film transistor 106 ofEmbodiment 1.

A thin film transistor of this embodiment and an embodiment of a methodfor manufacturing the thin film transistor are described using FIGS. 11Ato 11E.

FIGS. 11A to 11E illustrate an example of a cross-sectional structure ofa thin film transistor. A thin film transistor 310 shown in FIGS. 11A to11E is a kind of bottom-gate structure and is also referred to as aninverted staggered thin film transistor.

Although the thin film transistor 310 is described using a single-gatethin film transistor, a multi-gate thin film transistor including aplurality of channel formation regions can be formed as necessary.

Hereinafter, a process for manufacturing the thin film transistor 310over a substrate 300 is described using FIGS. 11A to 11E.

First, a conductive film is formed over the substrate 300 having aninsulating surface, and then, a first photolithography step isperformed, so that a gate electrode layer 311 is formed. Note that aresist mask may be formed by an inkjet method. Formation of the resistmask by an inkjet method needs no photomask; thus, manufacturing costcan be reduced.

Although there is no particular limitation on a substrate which can beused as the substrate 300 having an insulating surface, it is necessarythat the substrate 300 has at least heat resistance high enough towithstand heat treatment to be performed later.

For example, in the case where a glass substrate is used as thesubstrate 300, if the temperature of the heat treatment to be performedlater is high, it is preferable to use a glass substrate whose strainpoint is 730° C. or higher. As a material of the glass substrate, aglass material such as aluminosilicate glass, aluminoborosilicate glass,or barium borosilicate glass is used, for example. Note that bycontaining a larger amount of barium oxide (BaO) than boron oxide, aheat-resistant glass substrate which is of more practical use can beformed. Therefore, it is preferable that a glass substrate containingmore BaO than B₂O₃ be used.

Note that a substrate formed using an insulator such as a ceramicsubstrate, a quartz substrate, or a sapphire substrate may be usedinstead of the above-described glass substrate, as the substrate 300.Alternatively, a crystallized glass substrate or the like may be used.Further alternatively, a plastic substrate or the like may be used.

An insulating film which functions as a base film may be providedbetween the substrate 300 and the gate electrode layer 311. The basefilm has a function of preventing diffusion of an impurity element fromthe substrate 300, and can be formed with a single-layer structure or astacked-layer structure using one or more of a silicon nitride film, asilicon oxide film, a silicon nitride oxide film, and a siliconoxynitride film.

The gate electrode layer 311 can be formed to have a single-layer orstacked-layer structure using a metal material such as molybdenum,titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, orscandium, or an alloy material which contains any of these materials asits main component.

For example, as a two-layer structure of the gate electrode layer 311,any of the following structures is preferable: a two-layer structure ofan aluminum layer and a molybdenum layer stacked thereover, a two-layerstructure of a copper layer and a molybdenum layer stacked thereover, atwo-layer structure of a copper layer and a titanium nitride layer or atantalum nitride layer stacked thereover, a two-layer structure of atitanium nitride layer and a molybdenum layer, and a two-layer structureof a tungsten nitride layer and a tungsten layer stacked thereover. As athree-layer structure, a stack of a tungsten layer or a tungsten nitridelayer, a layer of an alloy of aluminum and silicon or an alloy ofaluminum and titanium, and a titanium nitride layer or a titanium layeris preferable.

Next, a gate insulating layer 302 is formed over the gate electrodelayer 311.

The gate insulating layer 302 can be formed with a single-layerstructure or a stacked-layer structure using one or more of a siliconoxide layer, a silicon nitride layer, a silicon oxynitride layer, asilicon nitride oxide layer, and an aluminum oxide layer by a plasma CVDmethod, a sputtering method, or the like. For example, a siliconoxynitride layer may be formed by a plasma CVD method using SiH₄,oxygen, and nitrogen as a deposition gas. In this embodiment, thethickness of the gate insulating layer 302 is greater than or equal to100 nm and less than or equal to 500 nm. In the case of a stacked-layerstructure, a first gate insulating layer with a thickness of 50 nm to200 nm and a second gate insulating layer with a thickness of 5 nm to300 nm are stacked on the first gate insulating layer.

In this embodiment, a silicon oxynitride layer having a thickness of 100nm or less is formed as the gate insulating layer 302 by a plasma CVDmethod.

Next, over the gate insulating layer 302, an oxide semiconductor film330 having a thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm isformed over the gate insulating layer 302. Note that appropriatethickness of the oxide semiconductor film varies depending on a materialthereof; therefore, the thickness may be determined as appropriatedepending on the material. A cross-sectional view at this stage is FIG.11A.

Note that before the oxide semiconductor film 330 is formed by asputtering method, it is preferable to perform reverse sputtering inwhich an argon gas is introduced and plasma is generated so that dust ona surface of the gate insulating layer 302 is removed. Instead of theargon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygenatmosphere, or the like may be used.

The oxide semiconductor film 330 is formed using an In—Ga—Zn—O-basedoxide semiconductor film, an In—Sn—Zn—O-based oxide semiconductor film,an In—Al—Zn—O-based oxide semiconductor film, a Sn—Ga—Zn—O-based oxidesemiconductor film, an Al—Ga—Zn—O-based oxide semiconductor film, aSn—Al—Zn—O-based oxide semiconductor film, an In—Zn—O-based oxidesemiconductor film, a Sn—Zn—O-based oxide semiconductor film, anAl—Zn—O-based oxide semiconductor film, an In—O-based oxidesemiconductor film, a Sn—O-based oxide semiconductor film, or aZn—O-based oxide semiconductor film. In this embodiment, the oxidesemiconductor film 330 is formed by a sputtering method using anIn—Ga—Zn—O-based oxide semiconductor target. Specifically, a targethaving a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 [mol %] (that is,In:Ga:Zn=1:1:0.5 [atom %]) is used. Alternatively, a target having acomposition ratio of In:Ga:Zn=1:1:1 [atom %] or In:Ga:Zn=1:1:2 [atom %]can be used. In this embodiment, the filling rate of the oxidesemiconductor target is equal to or greater than 90% and equal to orless than 100%, preferably equal to or greater than 95% and equal to orless than 99.9%. With use of the oxide semiconductor target having highfilling rate, the deposited oxide semiconductor film has high density.The target may contain SiO₂ at 2 wt % or more and 10 wt % or less.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide semiconductor film 330.

The sputtering is performed by holding the substrate in the chamber withpressure reduced at a substrate temperature of 100° C. to 600° C.,preferably 200° C. to 400° C. By heating the substrate in the filmdeposition, the concentration of impurities contained in the oxidesemiconductor film can be decreased. Further, damage by the sputteringcan be suppressed. Then, residual moisture in the chamber is removed, asputtering gas from which hydrogen and moisture are removed isintroduced, and the above-described target is used, so that the oxidesemiconductor film 330 is formed over the substrate 300. In order toremove residual moisture from the chamber, an adsorption-type vacuumpump is preferably used. For example, a cryopump, an ion pump, or atitanium sublimation pump is preferably used. As an exhaustion unit, aturbo molecular pump to which a cold trap is added may be used. In thechamber in which exhaustion is performed with the use of a cryopump, ahydrogen molecule, a compound including a hydrogen atom such as water(H₂O), a compound including a carbon atom, or the like, for example, isexhausted. Accordingly, the concentration of impurities included in theoxide semiconductor film formed in the chamber can be reduced.

As an example of the film deposition condition, the following conditionis employed: the distance between the substrate and the target is 100mm; the pressure is 0.6 Pa; the direct current (DC) power is 0.5 kW; andthe atmosphere is oxygen (the proportion of oxygen flow is 100%). It ispreferable that a pulsed direct current (DC) power source be usedbecause dust can be reduced and the film thickness can be made uniform.

Next, the oxide semiconductor film 330 is processed into anisland-shaped oxide semiconductor layer 331 by a second photolithographystep. A resist mask for forming the island-shaped oxide semiconductorlayer may be formed using an inkjet method. Formation of the resist maskby an inkjet method needs no photomask; thus, manufacturing cost can bereduced.

Next, a first heat treatment is performed on the oxide semiconductorlayer 331. The oxide semiconductor layer 331 can be dehydrated ordehydrogenated by the first heat treatment. The temperature of the firstheat treatment is higher than or equal to 400° C. and lower than orequal to 750° C., preferably higher than or equal to 400° C. and lowerthan the strain point of the substrate. In this embodiment, thesubstrate is put in an electric furnace which is a kind of heattreatment apparatus and heat treatment is performed on the oxidesemiconductor layer at 450° C. for 1 hour in a nitrogen atmosphere, andthen, water or hydrogen is prevented from entering the oxidesemiconductor layer, without exposure to the air; thus, the oxidesemiconductor layer 331 is obtained (see FIG. 11B).

The heat treatment apparatus is not limited to an electric furnace andmay be provided with a device that heats an object to be processed bythermal conduction or thermal radiation from a heater such as aresistance heater or the like. For example, an RTA (rapid thermalannealing) apparatus such as a GRTA (gas rapid thermal annealing)apparatus or an LRTA (lamp rapid thermal annealing) apparatus can beused. The LRTA apparatus is an apparatus for heating an object to beprocessed by radiation of light (an electromagnetic wave) emitted from alamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, acarbon arc lamp, a high pressure sodium lamp, or a high pressure mercurylamp. The GRTA apparatus is an apparatus for heat treatment using ahigh-temperature gas. As the gas, an inert gas which does not react byheat treatment with the object to be processed, like nitrogen or a raregas such as argon, is used.

For example, as the first heat treatment, GRTA may be performed asfollows: the substrate is transferred into an inert gas heated to a hightemperature of 650° C. to 700° C., heated for several minutes, andtransferred and taken out of the inert gas heated to the hightemperature. GRTA enables a high-temperature heat treatment in a shorttime.

In the first heat treatment, it is preferable that water, hydrogen, orthe like be not contained in nitrogen or a rare gas such as helium,neon, or argon. It is preferable that nitrogen or a rare gas such ashelium, neon, or argon which is introduced into the heat treatmentapparatus have a purity of 6N (99.9999%) or more, more preferably 7N(99.99999%) or more (that is, the concentration of impurities be 1 ppmor less, more preferably 0.1 ppm or less).

By the first heat treatment, hydrogen or the like contained in the oxidesemiconductor layer 331 can be removed, but at the same time, oxygendeficiency is caused, so that the oxide semiconductor layer 331 becomesan n-type semiconductor (a semiconductor with reduced resistance).Further, depending on the conditions of the first heat treatment or thematerial of the oxide semiconductor layer, the oxide semiconductor layer331 might be crystallized to be a microcrystalline film or apolycrystalline film. For example, the oxide semiconductor layer may becrystallized to be a microcrystalline oxide semiconductor film in whichthe degree of crystallization is 90% or more, or 80% or more. Further,depending on the conditions of the first heat treatment or the materialof the oxide semiconductor layer, the oxide semiconductor layer 331 maybe an amorphous oxide semiconductor film which does not containcrystalline components. The oxide semiconductor layer may become anoxide semiconductor film in which a microcrystalline portion (with agrain diameter of 1 nm to 20 nm, typically 2 nm to 4 nm) is mixed in anamorphous oxide semiconductor.

The first heat treatment of the oxide semiconductor layer can also beperformed on the oxide semiconductor film 330 before being processedinto the island-shaped oxide semiconductor layer. In that case, thesubstrate is taken out from the heat treatment apparatus after the firstheat treatment, and then a photolithography step is performed thereon.

The heat treatment which is effective for dehydration or dehydrogenationmay be performed after a source electrode and a drain electrode arestacked on the oxide semiconductor layer or after a protectiveinsulating film is formed over the source electrode and the drainelectrode as long as it is performed after the deposition of the oxidesemiconductor layer.

In the case where a contact hole is formed in the gate insulating layer302, a step thereof can be performed before or after the dehydration ordehydrogenation is performed on the oxide semiconductor film 330 or theoxide semiconductor layer 331.

The etching of the oxide semiconductor film is not limited to wetetching and may be dry etching.

The etching conditions (such as an etchant, etching time, ortemperature) are appropriately adjusted depending on a material so thatthe material can be etched into a desired shape.

Next, a conductive film is formed over the gate insulating layer 302 andthe oxide semiconductor layer 331. The conductive film may be formed bya sputtering method or a vacuum evaporation method. As a material of theconductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W,an alloy containing any of these elements as a component, an alloy filmcontaining any of these elements in combination, or the like can begiven. Further, one or more materials selected from manganese,magnesium, zirconium, beryllium, and yttrium may be used. Further, theconductive film may have a single-layer structure or a stacked-layerstructure of two or more layers. For example, a single-layer structureof an aluminum film including silicon, a two-layer structure in which atitanium film is stacked over an aluminum film, a three-layer structurein which a titanium film, an aluminum film, and a titanium film arestacked in this order, and the like can be given. Alternatively, a film,an alloy film, or a nitride film which contains aluminum (Al) and one ormore elements selected from titanium (Ti), tantalum (Ta), tungsten (W),molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) may beused.

In the case where heat treatment is performed after the deposition ofthe conductive film, it is preferable that the conductive film have heatresistance high enough to withstand the heat treatment.

A resist mask is formed over the conductive film by a thirdphotolithography step, and a source electrode layer 315 a and a drainelectrode layer 315 b are formed by selective etching, and then, theresist mask is removed (see FIG. 11C).

Light exposure at the time of the formation of the resist mask in thethird photolithography step is performed using ultraviolet light, KrFlaser light, or ArF laser light. The channel length L of a thin filmtransistor to be formed is determined by a distance between a lower endof the source electrode layer and a lower end of the drain electrodelayer, which are adjacent to each other over an oxide semiconductorlayer 331. In the case where light exposure is performed for a channellength L of less than 25 nm, the light exposure at the time of theformation of the resist mask in the third photolithography step isperformed using extreme ultraviolet light having an extremely shortwavelength of several nanometers to several tens of nanometers. In thelight exposure by extreme ultraviolet light, the resolution is high andthe focus depth is large. Accordingly, the channel length L of the thinfilm transistor can be made to be 10 nm to 1000 nm, the operation speedof a circuit can be increased, and low power consumption can be achievedby extremely small off-state current.

Note that each material and etching conditions are adjusted asappropriate such that the oxide semiconductor layer 331 is not removedby the etching of the conductive film.

In this embodiment, since a Ti film is used as the conductive film andthe In—Ga—Zn—O-based oxide semiconductor is used for the oxidesemiconductor layer 331, an ammonium hydrogen peroxide solution (a mixedsolution of ammonia, water, and a hydrogen peroxide solution) is used asan etchant.

In the third photolithography step, in some cases, part of the oxidesemiconductor layer 331 is etched, whereby an oxide semiconductor layerhaving a groove (a depression portion) may be formed. The resist maskused for forming the source electrode layer 315 a and the drainelectrode layer 315 b may be formed by an inkjet method. Formation ofthe resist mask by an inkjet method needs no photomask; thus,manufacturing cost can be reduced.

Further, an oxide conductive layer may be formed between the oxidesemiconductor layer and the source and drain electrode layers. The oxideconductive layer and the metal layer for forming the source and drainelectrode layers can be formed successively. The oxide conductive layercan function as a source region and a drain region.

By providing the oxide conductive layer as the source region and thedrain region between the oxide semiconductor layer and the source anddrain electrode layers, the resistance of the source region and thedrain region can be decreased and the transistor can be operated at highspeed.

In order to reduce the number of photomasks and steps in thephotolithography step, etching may be performed with the use of a resistmask formed using a multi-tone mask which is a light-exposure maskthrough which light is transmitted so as to have a plurality ofintensities. Since a resist mask formed using a multi-tone mask has aplurality of thicknesses and can be further changed in shape byperforming etching, the resist mask can be used in a plurality ofetching steps to provide different patterns. Therefore, a resist maskcorresponding to at least two kinds of different patterns can be formedby using one multi-tone mask. Thus, the number of light-exposure maskscan be reduced and the number of corresponding photolithography stepscan also be reduced, whereby simplification of the manufacturing processcan be realized.

Next, plasma treatment using a gas such as N₂O, N₂, or Ar is performed.By this plasma treatment, water or the like adsorbed on a surface of theoxide semiconductor layer which is exposed is removed. Plasma treatmentmay be performed using a mixed gas of oxygen and argon.

After the plasma treatment, an oxide insulating layer 316 whichfunctions as a protective insulating film and is in contact with part ofthe oxide semiconductor layer is formed without exposure to the air.

The oxide insulating layer 316 can be formed to a thickness of at least1 nm by a method by which an impurity such as water or hydrogen does notenter the oxide insulating layer 316, such as a sputtering method asappropriate. When hydrogen is contained in the oxide insulating layer316, entry of the hydrogen to the oxide semiconductor layer, orextraction of oxygen in the oxide semiconductor layer by hydrogen andoxygen deficiency may occur, thereby causing the backchannel of theoxide semiconductor layer to have lower resistance (to be n-type), sothat a parasitic channel may be formed. Therefore, it is important thata formation method in which hydrogen is not used is employed so that theoxide insulating layer 316 is formed containing as little hydrogen aspossible.

In this embodiment, a 200-nm-thick silicon oxide film is deposited asthe oxide insulating layer 316 by a sputtering method. The substratetemperature at the time of film deposition may be higher than or equalto room temperature and lower than or equal to 300° C., and in thisembodiment, is 100° C. The silicon oxide film can be formed by asputtering method in a rare gas (typically, argon) atmosphere, an oxygenatmosphere, or a mixed atmosphere containing a rare gas and oxygen. As atarget, a silicon oxide target or a silicon target may be used. Forexample, with the use of a silicon target, silicon oxide can bedeposited by a sputtering method in an atmosphere of oxygen andnitrogen. As the oxide insulating layer 316 which is formed in contactwith the oxide semiconductor layer whose resistance is reduced, aninorganic insulating film which does not include impurities such asmoisture, a hydrogen ion, or OH⁻ and blocks the entry of theseimpurities from the outside is used. Typically, a silicon oxide film, asilicon oxynitride film, an aluminum oxide film, an aluminum oxynitridefilm, or the like is used.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide insulating layer 316. This is inorder to prevent the oxide semiconductor layer 331 and the oxideinsulating layer 316 from containing hydrogen, a hydroxyl group, ormoisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxideinsulating layer 316 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide insulating layer 316.

Next, a second heat treatment (preferably at a temperature of 200° C. to400° C., for example, at a temperature of 250° C. to 350° C.) isperformed in an inert gas atmosphere or an oxygen gas atmosphere. Forexample, the second heat treatment is performed at 250° C. for 1 hour ina nitrogen atmosphere. With the second heat treatment, heat is appliedin a state where part of the oxide semiconductor layer (the channelformation region) is in contact with the oxide insulating layer 316.

Through the above process, heat treatment for dehydration ordehydrogenation is performed on the deposited oxide semiconductor filmto decrease the resistance, and thus, a part of the oxide semiconductorfilm is selectively made to include excessive oxygen. As a result, achannel formation region 313 overlapping the gate electrode layer 311becomes i-type, and a high-resistance source region 314 a which overlapsthe source electrode layer 315 a and which is formed using thelow-resistance oxide semiconductor and a high-resistance drain region314 b which overlaps the drain electrode layer 315 b and which is formedusing the low-resistance oxide semiconductor are formed in aself-aligned manner. Through the above steps, the thin film transistor310 is formed (see FIG. 11D).

Furthermore, heat treatment may be performed at a temperature of 100° C.to 200° C. in the air for 1 hour to 30 hours. In this embodiment, heattreatment is performed at 150° C. for 10 hours. This heat treatment maybe performed at a fixed heating temperature. Alternatively, thefollowing change in the heating temperature may be conducted pluraltimes repeatedly: the heating temperature is increased from roomtemperature to a temperature of 100° C. to 200° C. and then decreased toroom temperature. Further, this heat treatment may be performed under areduced pressure before the formation of the oxide insulating film.Under the reduced pressure, the heat treatment time can be shortened.With this heat treatment, hydrogen is introduced from the oxidesemiconductor layer to the oxide insulating layer; thus, a normally-offthin film transistor can be obtained. Therefore, reliability of theliquid crystal display device can be improved. Further, by using asilicon oxide layer containing many defects as the oxide insulatinglayer, impurities such as hydrogen, moisture, a hydroxyl group, orhydride contained in the oxide semiconductor layer are diffused into theoxide insulating layer by this heat treatment to further reduce theimpurities contained in the oxide semiconductor layer.

The high-resistance drain region 314 b (or the high-resistance sourceregion 314 a) is formed in a portion of the oxide semiconductor layerwhich overlaps the drain electrode layer 315 b (or the source electrodelayer 315 a), so that the reliability of the thin film transistor can beincreased. Specifically, by the formation of the high-resistance drainregion 314 b, the conductivity can gradually changes from the drainelectrode layer 315 b to the high-resistance drain region 314 b and thechannel formation region 313 in the transistor. Therefore, in the casewhere the thin film transistor operates using the drain electrode layer315 b connected to a wiring for supplying a high power supply potentialVDD, the high-resistance drain region serves as a buffer and a highelectric field is not applied locally even if a high electric field isapplied between the gate electrode layer 311 and the drain electrodelayer 315 b, so that the withstand voltage of the transistor can beimproved.

The high-resistance source region or the high-resistance drain regionmay be formed entirely in the film thickness direction in the oxidesemiconductor layer in the case where the oxide semiconductor layer isas thin as 15 nm or less; whereas in the case where the oxidesemiconductor layer is as thick as 30 nm to 50 nm, the resistance ofpart of the oxide semiconductor layer, that is, a region of the oxidesemiconductor layer, which is in contact with the source or drainelectrode layer and the vicinity thereof may be decreased, so that thehigh-resistance source region or the high-resistance drain region isformed and a region of the oxide semiconductor layer which is near thegate insulating layer can be made to be i-type.

A protective insulating layer may be formed over the oxide insulatinglayer 316. For example, a silicon nitride film is formed by an RFsputtering method. An RF sputtering method is preferable as a method forforming a protective insulating layer because it has high productivity.As the protective insulating layer, an inorganic insulating film whichdoes not contain impurities such as moisture, a hydrogen ion, or OH⁻ andblocks the entry of these impurities from the outside is used; a siliconnitride film, an aluminum nitride film, a silicon nitride oxide film, analuminum nitride oxide film, or the like is used. In this embodiment, aprotective insulating layer 303 is formed using a silicon nitride filmas the protective insulating layer (see FIG. 11E).

As the protective insulating layer 303 in this embodiment, a siliconnitride film is formed by heating the substrate 300, over which layersup to and including the oxide insulating layer 316 are formed, to atemperature of 100° C. to 400° C., introducing a sputtering gascontaining high-purity nitrogen from which hydrogen and moisture areremoved, and using a target of silicon semiconductor. In that case, itis also preferable that residual moisture be removed from the treatmentchamber in the formation of the protective insulating layer 303 as isthe case of the oxide insulating layer 316.

A planarization insulating layer for planarization may be provided overthe protective insulating layer 303.

In a plurality of pixels of a display portion of a liquid crystaldisplay device including the thin film transistor using the oxidesemiconductor layer, off-state current can be reduced. Accordingly, aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 7

In this embodiment, another example of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. A thin film transistor 360 described inthis embodiment can be used as the thin film transistor 106 ofEmbodiment 1.

A thin film transistor of this embodiment and an embodiment of a methodfor manufacturing the thin film transistor are described using FIGS. 12Ato 12D.

FIGS. 12A to 12D illustrate an example of a cross-sectional structure ofa thin film transistor. The thin film transistor 360 shown in FIGS. 12Ato 12D is a kind of bottom-gate structure which is called a channelprotective type (also called a channel stop type), and is also referredto as an inverted staggered thin film transistor.

Although the thin film transistor 360 is described using a single-gatethin film transistor, a multi-gate thin film transistor including aplurality of channel formation regions can be formed as necessary.

Hereinafter, a process for manufacturing the thin film transistor 360over a substrate 320 is described using FIGS. 12A to 12D.

First, a conductive film is formed over the substrate 320 having aninsulating surface, a first photolithography step is performed to form aresist mask, and the conductive film is selectively etched by using theresist mask, so that a gate electrode layer 361 is formed. After that,the resist mask is removed. Note that the resist mask may be formed byan inkjet method. Formation of the resist mask by an inkjet method needsno photomask; thus, manufacturing cost can be reduced.

The gate electrode layer 361 can be formed to have a single-layer orstacked-layer structure using a metal material such as molybdenum,titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, orscandium, or an alloy material which contains any of these materials asits main component.

Next, a gate insulating layer 322 is formed over the gate electrodelayer 361.

In this embodiment, a silicon oxynitride layer having a thickness of 100nm or less is formed as the gate insulating layer 322 by a plasma CVDmethod.

Next, an oxide semiconductor film having a thickness of 2 nm to 200 nmis formed over the gate insulating layer 322, and is processed into anisland-shaped oxide semiconductor layer by a second photolithographystep. In this embodiment, the oxide semiconductor film is formed by asputtering method using an In—Ga—Zn—O-based oxide semiconductor target.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide semiconductor film. This is inorder to prevent the oxide semiconductor film from containing hydrogen,a hydroxyl group, or moisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxidesemiconductor film formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide semiconductor film.

Next, the oxide semiconductor layer is dehydrated or dehydrogenated. Thetemperature of the first heat treatment for the dehydration ordehydrogenation is higher than or equal to 400° C. and lower than orequal to 750° C., preferably higher than or equal to 400° C. and lowerthan the strain point of the substrate. In this embodiment, thesubstrate is put in an electric furnace which is a kind of heattreatment apparatus and heat treatment is performed on the oxidesemiconductor layer at 450° C. for 1 hour in a nitrogen atmosphere, andthen, water or hydrogen is prevented from entering the oxidesemiconductor layer, without exposure to the air; thus, an oxidesemiconductor layer 332 is obtained (see FIG. 12A).

Next, plasma treatment using a gas such as N₂O, N₂, or Ar is performed.By this plasma treatment, water or the like adsorbed on a surface of theoxide semiconductor layer which is exposed is removed. Plasma treatmentmay be performed using a mixed gas of oxygen and argon.

Next, an oxide insulating layer is formed over the gate insulating layer322 and the oxide semiconductor layer 332. After that, a resist mask isformed by a third photolithography step, and an oxide insulating layer366 is formed by selective etching. After that, the resist mask isremoved.

In this embodiment, a 200-nm-thick silicon oxide film is deposited asthe oxide insulating layer 366 by a sputtering method. The substratetemperature at the time of film deposition may be higher than or equalto room temperature and lower than or equal to 300° C., and in thisembodiment, is 100° C. The silicon oxide film can be formed by asputtering method in a rare gas (typically, argon) atmosphere, an oxygenatmosphere, or a mixed atmosphere containing a rare gas and oxygen. As atarget, a silicon oxide target or a silicon target may be used. Forexample, with the use of a silicon target, silicon oxide can bedeposited by a sputtering method in an atmosphere of oxygen andnitrogen. As the oxide insulating layer 366 which is formed in contactwith the oxide semiconductor layer, an inorganic insulating film whichdoes not include impurities such as moisture, a hydrogen ion, or OH⁻ andblocks the entry of these impurities from the outside is used.Typically, a silicon oxide film, a silicon oxynitride film, an aluminumoxide film, an aluminum oxynitride film, or the like is used.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide insulating layer 366. This is inorder to prevent the oxide semiconductor layer 332 and the oxideinsulating layer 366 from containing hydrogen, a hydroxyl group, ormoisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxideinsulating layer 366 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide insulating layer 366.

Next, a second heat treatment (preferably at a temperature of 200° C. to400° C., for example, at a temperature of 250° C. to 350° C.) may beperformed in an inert gas atmosphere or an oxygen gas atmosphere. Forexample, the second heat treatment is performed at 250° C. for 1 hour ina nitrogen atmosphere. With the second heat treatment, heat is appliedin a state where part of the oxide semiconductor layer (the channelformation region) is in contact with the oxide insulating layer 366.

In this embodiment, the oxide semiconductor layer 332 which is providedwith the oxide insulating layer 366 and is partly exposed is furthersubjected to heat treatment in a nitrogen atmosphere or an inert gasatmosphere or under a reduced pressure. By the heat treatment in anitrogen atmosphere or an inert gas atmosphere or under a reducedpressure, the resistance of the exposed region of the oxidesemiconductor layer 332, which is not covered by the oxide insulatinglayer 366, can be decreased. For example, heat treatment is performed at250° C. for 1 hour in a nitrogen atmosphere.

With the heat treatment of the oxide semiconductor layer 332 providedwith the oxide insulating layer 366 in a nitrogen atmosphere, theresistance of the exposed region of the oxide semiconductor layer 332 isdecreased, so that an oxide semiconductor layer 362 including regionswith different resistances (indicated as a shaded region and a whiteregion in FIG. 12B) is formed.

Next, after a conductive film is formed over the gate insulating layer322, the oxide semiconductor layer 362, and the oxide insulating layer366, a resist mask is formed over the conductive film by a fourthphotolithography step, and a source electrode layer 365 a and a drainelectrode layer 365 b are formed by selective etching, and then, theresist mask is removed (see FIG. 12C).

As a material of the source electrode layer 365 a and the drainelectrode layer 365 b, an element selected from Al, Cr, Cu, Ta, Ti, Mo,and W, an alloy containing any of these elements as a component, analloy film containing any of these elements in combination, or the likecan be given. Further, the source electrode layer 365 a and the drainelectrode layer 365 b may have a single-layer structure or astacked-layer structure of two or more layers.

Through the above process, a part of the oxide semiconductor film isselectively made to include excessive oxygen. As a result, a channelformation region 363 overlapping the gate electrode layer 361 becomesi-type, and a high-resistance source region 364 a which overlaps thesource electrode layer 365 a and a high-resistance drain region 364 bwhich overlaps the drain electrode layer 365 b are formed in aself-aligned manner. Through the above steps, the thin film transistor360 is formed.

Furthermore, heat treatment may be performed at a temperature of 100° C.to 200° C. in the air for 1 hour to 30 hours. In this embodiment, heattreatment is performed at 150° C. for 10 hours. This heat treatment maybe performed at a fixed heating temperature. Alternatively, thefollowing change in the heating temperature may be conducted pluraltimes repeatedly: the heating temperature is increased from roomtemperature to a temperature of 100° C. to 200° C. and then decreased toroom temperature. Further, this heat treatment may be performed under areduced pressure before the formation of the oxide insulating film.Under the reduced pressure, the heat treatment time can be shortened.With this heat treatment, hydrogen is introduced from the oxidesemiconductor layer to the oxide insulating layer; thus, a normally-offthin film transistor can be obtained. Therefore, reliability of theliquid crystal display device can be improved.

The high-resistance drain region 364 b (or the high-resistance sourceregion 364 a) which is formed using the low-resistance oxidesemiconductor is formed in a portion of the oxide semiconductor layerwhich overlaps the drain electrode layer 365 b (or the source electrodelayer 365 a), so that the reliability of the thin film transistor can beincreased. Specifically, by the formation of the high-resistance drainregion 364 b, the conductivity can gradually changes from the drainelectrode layer 365 b to the high-resistance drain region 364 b and thechannel formation region 363 in the transistor. Therefore, in the casewhere the thin film transistor operates using the drain electrode layer365 b connected to a wiring for supplying a high power supply potentialVDD, the high-resistance drain region serves as a buffer and a highelectric field is not applied locally even if a high electric field isapplied between the gate electrode layer 361 and the drain electrodelayer 365 b, so that the withstand voltage of the transistor can beimproved.

A protective insulating layer 323 is formed over the source electrodelayer 365 a, the drain electrode layer 365 b, and the oxide insulatinglayer 366. In this embodiment, the protective insulating layer 323 isformed using a silicon nitride film (see FIG. 12D).

Note that an oxide insulating layer may be formed over the sourceelectrode layer 365 a, the drain electrode layer 365 b, and the oxideinsulating layer 366, and the protective insulating layer 323 may bestacked over the oxide insulating layer.

In a plurality of pixels of a display portion of a liquid crystaldisplay device including the thin film transistor using the oxidesemiconductor layer, off-state current can be reduced. Accordingly, aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 8

In this embodiment, another example of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. A thin film transistor 350 described inthis embodiment can be used as the thin film transistor 106 ofEmbodiment 1.

A thin film transistor of this embodiment and an embodiment of a methodfor manufacturing the thin film transistor are described using FIGS. 13Ato 13D.

Although the thin film transistor 350 is described using a single-gatethin film transistor, a multi-gate thin film transistor including aplurality of channel formation regions can be formed as necessary.

Hereinafter, a process for manufacturing the thin film transistor 350over a substrate 340 is described using FIGS. 13A to 13D.

First, a conductive film is formed over the substrate 340 having aninsulating surface, and then, a first photolithography step isperformed, so that a gate electrode layer 351 is formed. In thisembodiment, a 150-nm-thick tungsten film is formed as the gate electrodelayer 351 by a sputtering method.

Next, a gate insulating layer 342 is formed over the gate electrodelayer 351. In this embodiment, a silicon oxynitride layer having athickness of 100 nm or less is formed as the gate insulating layer 342by a plasma CVD method.

Next, a conductive film is formed over the gate insulating layer 342; aresist mask is formed over the conductive film by a secondphotolithography step; a source electrode layer 355 a and a drainelectrode layer 355 b are formed by selective etching, and then, theresist mask is removed (see FIG. 13A).

Next, an oxide semiconductor film 345 is formed (see FIG. 13B). In thisembodiment, the oxide semiconductor film 345 is formed by a sputteringmethod using an In—Ga—Zn—O-based oxide semiconductor target. The oxidesemiconductor film 345 is processed into an island-shaped oxidesemiconductor layer by a third photolithography step.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide semiconductor film 345. This isin order to prevent the oxide semiconductor film 345 from containinghydrogen, a hydroxyl group, or moisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxidesemiconductor film 345 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide semiconductor film 345.

Next, the oxide semiconductor layer is dehydrated or dehydrogenated. Thetemperature of the first heat treatment for the dehydration ordehydrogenation is higher than or equal to 400° C. and lower than orequal to 750° C., preferably higher than or equal to 400° C. and lowerthan the strain point of the substrate. In this embodiment, thesubstrate is put in an electric furnace which is a kind of heattreatment apparatus and heat treatment is performed on the oxidesemiconductor layer at 450° C. for 1 hour in a nitrogen atmosphere, andthen, water or hydrogen is prevented from entering the oxidesemiconductor layer, without exposure to the air; thus, an oxidesemiconductor layer 346 is obtained (see FIG. 13C).

As the first heat treatment, GRTA may be performed as follows: thesubstrate is transferred into an inert gas heated to a high temperatureof 650° C. to 700° C., heated for several minutes, and transferred andtaken out of the inert gas heated to the high temperature. GRTA enablesa high-temperature heat treatment in a short time.

An oxide insulating layer 356 serving as a protective insulating film isformed in contact with the oxide semiconductor layer 346.

The oxide insulating layer 356 can be formed to a thickness of at least1 nm by a method by which an impurity such as water or hydrogen does notenter the oxide insulating layer 356, such as a sputtering method asappropriate. When hydrogen is contained in the oxide insulating layer356, entry of the hydrogen to the oxide semiconductor layer, orextraction of oxygen in the oxide semiconductor layer by hydrogen andoxygen deficiency may occur, thereby causing the backchannel of theoxide semiconductor layer to have lower resistance (to be n-type), sothat a parasitic channel may be formed. Therefore, it is important thata formation method in which hydrogen is not used is employed so that theoxide insulating layer 356 is formed containing as little hydrogen aspossible.

In this embodiment, a 200-nm-thick silicon oxide film is deposited asthe oxide insulating layer 356 by a sputtering method. The substratetemperature at the time of film deposition may be higher than or equalto room temperature and lower than or equal to 300° C., and in thisembodiment, is 100° C. The silicon oxide film can be formed by asputtering method in a rare gas (typically, argon) atmosphere, an oxygenatmosphere, or a mixed atmosphere containing a rare gas and oxygen. As atarget, a silicon oxide target or a silicon target may be used. Forexample, with the use of a silicon target, silicon oxide can bedeposited by a sputtering method in an atmosphere of oxygen andnitrogen. As the oxide insulating layer 356 which is formed in contactwith the oxide semiconductor layer, an inorganic insulating film whichdoes not include impurities such as moisture, a hydrogen ion, or OH⁻ andblocks the entry of these impurities from the outside is used.Typically, a silicon oxide film, a silicon oxynitride film, an aluminumoxide film, an aluminum oxynitride film, or the like is used.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide insulating layer 356. This is inorder to prevent the oxide semiconductor layer 346 and the oxideinsulating layer 356 from containing hydrogen, a hydroxyl group, ormoisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxideinsulating layer 356 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide insulating layer 356.

Next, a second heat treatment (preferably at a temperature of 200° C. to400° C., for example, at a temperature of 250° C. to 350° C.) isperformed in an inert gas atmosphere or an oxygen gas atmosphere. Forexample, the second heat treatment is performed at 250° C. for 1 hour ina nitrogen atmosphere. With the second heat treatment, heat is appliedin a state where part of the oxide semiconductor layer (the channelformation region) is in contact with the oxide insulating layer 356.

Through the above process, the oxide semiconductor film is made toinclude excessive oxygen. As a result, an i-type oxide semiconductorlayer 352 is formed. Through the above steps, the thin film transistor350 is formed.

Furthermore, heat treatment may be performed at a temperature of 100° C.to 200° C. in the air for 1 hour to 30 hours. In this embodiment, heattreatment is performed at 150° C. for 10 hours. This heat treatment maybe performed at a fixed heating temperature. Alternatively, thefollowing change in the heating temperature may be conducted pluraltimes repeatedly: the heating temperature is increased from roomtemperature to a temperature of 100° C. to 200° C. and then decreased toroom temperature. Further, this heat treatment may be performed under areduced pressure before the formation of the oxide insulating film.Under the reduced pressure, the heat treatment time can be shortened.With this heat treatment, hydrogen is introduced from the oxidesemiconductor layer to the oxide insulating layer; thus, a normally-offthin film transistor can be obtained. Therefore, reliability of theliquid crystal display device can be improved.

A protective insulating layer may be formed over the oxide insulatinglayer 356. For example, a silicon nitride film is formed by an RFsputtering method. In this embodiment, a protective insulating layer 343is formed using a silicon nitride film as the protective insulatinglayer (see FIG. 13D).

A planarization insulating layer for planarization may be provided overthe protective insulating layer 343.

In a plurality of pixels of a display portion of a liquid crystaldisplay device including the thin film transistor using the oxidesemiconductor layer, off-state current can be reduced. Accordingly, aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 9

In this embodiment, another example of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. A thin film transistor 380 described inthis embodiment can be used as the thin film transistor 106 ofEmbodiment 1.

In this embodiment, an example which is different from Embodiment 6 inpart of the manufacturing process of a thin film transistor will bedescribed using FIG. 14. Since FIG. 14 is the same as FIGS. 11A to 11Eexcept for part of the process, the same reference numerals are used forthe same portions, and detailed description of the same portions is notrepeated.

In accordance with Embodiment 6, a gate electrode layer 381 is formedover a substrate 370, and a first gate insulating layer 372 a and asecond gate insulating layer 372 b are stacked. In this embodiment, agate insulating layer has a two-layer structure, in which a nitrideinsulating layer is used as the first gate insulating layer 372 a and anoxide insulating layer is used as the second gate insulating layer 372b.

As the oxide insulating layer, a silicon oxide layer, a siliconoxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer,or the like can be used. As the nitride insulating layer, a siliconnitride layer, a silicon nitride oxide layer, an aluminum nitride layer,an aluminum nitride oxide layer, or the like can be used.

In the structure of this embodiment, a silicon nitride layer and asilicon oxide layer are stacked in this order over the gate electrodelayer 381. For example, a 150-nm-thick gate insulating layer is formedin such a manner that a silicon nitride layer (SiN_(y) (y>0)) having athickness of 50 nm to 200 nm (in this embodiment, 50 nm) is formed by asputtering method as the first gate insulating layer 372 a and then asilicon oxide layer (SiO_(x) (x>0)) having a thickness of 5 nm to 300 nm(in this embodiment, 100 nm) is stacked as the second gate insulatinglayer 372 b over the first gate insulating layer 372 a.

Next, an oxide semiconductor film is formed and is processed into anisland-shaped oxide semiconductor layer by a photolithography step. Inthis embodiment, the oxide semiconductor film is formed by a sputteringmethod using an In—Ga—Zn—O-based oxide semiconductor target.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide semiconductor film. This is inorder to prevent the oxide semiconductor film from containing hydrogen,a hydroxyl group, or moisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxidesemiconductor film formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide semiconductor film.

Next, the oxide semiconductor layer is dehydrated or dehydrogenated. Thetemperature of the first heat treatment for the dehydration ordehydrogenation is higher than or equal to 400° C. and lower than orequal to 750° C., preferably higher than or equal to 425° C. Note thatin the case where the temperature of the first heat treatment is 425° C.or higher, the heat treatment time may be one hour or less, while in thecase where the temperature of the first heat treatment is lower than425° C., the heat treatment time is set to more than one hour. In thisembodiment, the substrate is put in an electric furnace which is a kindof heat treatment apparatus and heat treatment is performed on the oxidesemiconductor layer in a nitrogen atmosphere, and then, water orhydrogen is prevented from entering the oxide semiconductor layer,without exposure to the air; thus, an oxide semiconductor layer isobtained. After that, cooling is performed by introduction of ahigh-purity oxygen gas, a high-purity N₂O gas, or ultra-dry air (havinga dew point of −40° C. or lower, preferably −60° C. or lower) into thesame furnace. It is preferable that the oxygen gas or the N₂O gas do notcontain water, hydrogen, or the like. Alternatively, the purity of anoxygen gas or an N₂O gas which is introduced into the heat treatmentapparatus is preferably 6N (99.9999%) or higher, more preferably 7N(99.99999%) or higher (that is, the concentration of impurities in theoxygen gas or the N₂O gas is 1 ppm or less, preferably 0.1 ppm or less).

Note that the heat treatment apparatus is not limited to an electricfurnace. For example, an RTA (rapid thermal annealing) apparatus such asa GRTA (gas rapid thermal annealing) apparatus or an LRTA (lamp rapidthermal annealing) apparatus can be used. The LRTA apparatus is anapparatus for heating an object to be processed by radiation of light(an electromagnetic wave) emitted from a lamp such as a halogen lamp, ametal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressuresodium lamp, or a high pressure mercury lamp. The LRTA apparatus may beprovided with not only a lamp but also a device that heats an object tobe processed by thermal conduction or thermal radiation from a heatersuch as a resistance heater or the like. GRTA is a method for heattreatment using a high-temperature gas. As the gas, an inert gas whichdoes not react by heat treatment with the object to be processed, likenitrogen or a rare gas such as argon, is used. The heat treatment may beperformed at 600° C. to 750° C. for several minutes by an RTA method.

After the first heat treatment for dehydration or dehydrogenation, heattreatment may be performed at a temperature of 200° C. to 400° C.,preferably 200° C. to 300° C., in an oxygen gas atmosphere or a N₂O gasatmosphere.

The first heat treatment of the oxide semiconductor layer can also beperformed on the oxide semiconductor film before being processed intothe island-shaped oxide semiconductor layer. In that case, the substrateis taken out from the heat treatment apparatus after the first heattreatment, and then a photolithography step is performed thereon.

The entire oxide semiconductor film is made to contain an excess amountof oxygen through the above steps, whereby the oxide semiconductor filmhas higher resistance, that is, becomes i-type. Accordingly, an oxidesemiconductor layer 382 whose entire region is i-type is formed.

Next, a conductive film is formed over the oxide semiconductor layer382. After that, a resist mask is formed by a photolithography step, andselective etching is performed to form a source electrode layer 385 aand a drain electrode layer 385 b, and then, an oxide insulating layer386 is formed by a sputtering method.

In that case, it is preferable to remove residual moisture in thechamber in the deposition of the oxide insulating layer 386. This is inorder to prevent the oxide semiconductor layer 382 and the oxideinsulating layer 386 from containing hydrogen, a hydroxyl group, ormoisture.

In order to remove residual moisture from the chamber, anadsorption-type vacuum pump is preferably used. For example, a cryopump,an ion pump, or a titanium sublimation pump is preferably used. As anexhaustion unit, a turbo molecular pump to which a cold trap is addedmay be used. In the chamber in which exhaustion is performed with theuse of a cryopump, a hydrogen molecule, a compound including a hydrogenatom such as water (H₂O), or the like, for example, is exhausted.Accordingly, the concentration of impurities included in the oxideinsulating layer 386 formed in the chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is removed to 1 ppm orless, preferably 10 ppb or less be used as the sputtering gas for thedeposition of the oxide insulating layer 386.

Through the above steps, the thin film transistor 380 can be formed.

Next, heat treatment (preferably at a temperature higher than or equalto 150° C. and lower than 350° C.) may be performed in an inert gasatmosphere or a nitrogen gas atmosphere in order to suppress variationof electrical characteristics of the thin film transistor. For example,heat treatment is performed at 250° C. for 1 hour in a nitrogenatmosphere.

In addition, heat treatment may be performed at a temperature of 100° C.to 200° C. in the air for 1 hour to 30 hours. In this embodiment, heattreatment is performed at 150° C. for 10 hours. This heat treatment maybe performed at a fixed heating temperature. Alternatively, thefollowing change in the heating temperature may be conducted pluraltimes repeatedly: the heating temperature is increased from roomtemperature to a temperature of 100° C. to 200° C. and then decreased toroom temperature. Further, this heat treatment may be performed under areduced pressure before the formation of the oxide insulating film.Under the reduced pressure, the heat treatment time can be shortened.With this heat treatment, hydrogen is introduced from the oxidesemiconductor layer to the oxide insulating layer; thus, a normally-offthin film transistor can be obtained. Therefore, reliability of theliquid crystal display device can be improved.

A protective insulating layer 373 is formed over the oxide insulatinglayer 386. In this embodiment, a 100-nm-thick silicon nitride film isformed as the protective insulating layer 373 by a sputtering method.

The protective insulating layer 373 and the first gate insulating layer372 a, which are nitride insulating layers, do not contain impuritiessuch as moisture, hydrogen, hydride, or hydroxide and has theadvantageous effect of preventing the entry of these impurities from theoutside.

Therefore, in the manufacturing process after the formation of theprotective insulating layer 373, the entry of impurities such asmoisture from the outside can be prevented. Further, even after a deviceis completed as a liquid crystal display device, the entry of impuritiessuch as moisture from the outside can be prevented in the long term;therefore, long-term reliability of the device can be improved.

The insulating layers provided between the protective insulating layer373 and the first gate insulating layer 372 a which are nitrideinsulating layers may be removed to make the protective insulating layer373 in contact with the first gate insulating layer 372 a.

Accordingly, impurities such as moisture, hydrogen, hydride, orhydroxide in the oxide semiconductor layer can be reduced to the minimumand the re-entry thereof can be prevented, so that the concentration ofimpurities in the oxide semiconductor layer can be kept low.

A planarization insulating layer for planarization may be provided overthe protective insulating layer 373.

In a plurality of pixels of a display portion of a liquid crystaldisplay device including the thin film transistor using the oxidesemiconductor layer, off-state current can be reduced. Accordingly, aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 10

In this embodiment, another example of a thin film transistor which canbe applied to a liquid crystal display device disclosed in thisspecification will be described. A thin film transistor described inthis embodiment can be applied to the thin film transistors ofEmbodiment 2 to 8.

In this embodiment, an example of using a conductive material having alight transmitting property for a gate electrode layer, a sourceelectrode layer, and a drain electrode layer will be described. Notethat the other part of this embodiment is similar to the aboveembodiments, and the description of the same portions as and theportions and steps having functions similar to those in the aboveembodiments is not repeated. Further, a specific description for thesame portions is omitted.

As a material of a gate electrode layer, a source electrode layer, and adrain electrode layer, a conductive material that transmits visiblelight can be used. For example, any of the following metal oxides can beused: an In—Sn—O-based metal oxide; an In—Sn—Zn—O-based metal oxide; anIn—Al—Zn—O-based metal oxide; a Sn—Ga—Zn—O-based metal oxide; anAl—Ga—Zn—O-based metal oxide; a Sn—Al—Zn—O-based metal oxide; anIn—Zn—O-based metal oxide; a Sn—Zn—O-based metal oxide; an Al—Zn—O-basedmetal oxide; an In—O-based metal oxide; a Sn—O-based metal oxide; and aZn—O-based metal oxide. The thickness thereof is set in the range of 50nm to 300 nm as appropriate. As a deposition method of the metal oxideused for the gate electrode layer, the source electrode layer, and thedrain electrode layer, a sputtering method, a vacuum evaporation method(an electron beam evaporation method or the like), an arc discharge ionplating method, or a spray method is used. In the case where asputtering method is employed, it is preferable that deposition beperformed using a target containing SiO₂ at 2 wt % to 10 wt % and SiOx(x>0) which inhibits crystallization be contained in the lighttransmitting conductive film so as to prevent crystallization at thetime of heat treatment in a later step.

Note that the unit of the percentage of components in the lighttransmitting conductive film is atomic percent, and the percentage ofcomponents is evaluated by analysis using an electron probe X-raymicroanalyzer (EPMA).

In a pixel provided with a thin film transistor, when a pixel electrodelayer, another electrode layer (such as a capacitor electrode layer), ora wiring layer (such as a capacitor wiring layer) is formed using aconductive film that transmits visible light, a display device havinghigh aperture ratio can be realized. Needless to say, it is preferablethat a gate insulating layer, an oxide insulating layer, a protectiveinsulating layer, and a planarization insulating layer in the pixel bealso each formed using a film that transmits visible light.

In this specification, a film that transmits visible light means a filmhaving such a thickness as to have a visible light transmittance of 75%to 100%. In the case where the film has conductivity, the film is alsoreferred to as a transparent conductive film. Further, a conductive filmwhich is semi-transmissive with respect to visible light may be used asmetal oxide applied to the gate electrode layer, the source electrodelayer, the drain electrode layer, the pixel electrode layer, anotherelectrode layer, or another wiring layer. The conductive film which issemi-transmissive with respect to visible light refers to a film havinga visible light transmittance of 50% to 75%.

When a thin film transistor has a light transmitting property, theaperture ratio can be increased. For small-size liquid crystal displaypanels of 10 inches or smaller in particular, a high aperture ratio canbe achieved even when the size of pixels is decreased in order torealize higher resolution of display images by increasing the number ofgate wirings, for example. Further, by using a film having a lighttransmitting property for components of a thin film transistor, a highaperture ratio can be achieved even when one pixel is divided into aplurality of sub-pixels in order to realize a wide viewing angle. Thatis, a high aperture ratio can be obtained even when a high-density groupof thin film transistors is provided, so that a sufficient area of adisplay region can be secured. For example, in the case where one pixelincludes two to four sub-pixels, an aperture ratio can be improvedbecause the thin film transistor has a light transmitting property.Further, a storage capacitor may be formed using the same material andin the same step as the component in the thin film transistor so thatthe storage capacitor can have a light transmitting property, wherebythe aperture ratio can be further improved.

This embodiment can be implemented in appropriate combination with anyof other embodiments.

Embodiment 11

The appearance and the cross section of a liquid crystal display panel,which is an embodiment of a liquid crystal display device, are describedwith reference to FIGS. 15A to 15C. FIGS. 15A and 15C are each a topview of a panel in which thin film transistors 4010 and 4011 and aliquid crystal element 4013, which are formed over a first substrate4001, are sealed between the first substrate 4001 and a second substrate4006 with a sealant 4505. FIG. 15B corresponds to a cross-sectional viewof FIG. 15A or 15C along line M-N.

The sealant 4005 is provided so as to surround a pixel portion 4002 anda scan line driver circuit 4004 which are provided over the firstsubstrate 4001. The second substrate 4006 is provided over the pixelportion 4002 and the scan line driver circuit 4004. Therefore, the pixelportion 4002 and the scan line driver circuit 4004 are sealed togetherwith a liquid crystal layer 4008, by the first substrate 4001, thesealant 4005, and the second substrate 4006. A signal line drivercircuit 4003 that is formed using a single crystal semiconductor film ora polycrystalline semiconductor film over a substrate separatelyprepared is mounted in a region that is different from the regionsurrounded by the sealant 4005 over the first substrate 4001.

Note that a connection method of a driver circuit which is separatelyformed is not particularly limited, and a COG method, a wire bondingmethod, a TAB method, or the like can be used. FIG. 15A illustrates anexample of mounting the signal line driver circuit 4003 by a COG method,and FIG. 15C illustrates an example of mounting the signal line drivercircuit 4003 by a TAB method.

Further, the pixel portion 4002 and the scan line driver circuit 4004provided over the first substrate 4001 each include a plurality of thinfilm transistors. FIG. 15B illustrates the thin film transistor 4010included in the pixel portion 4002 and the thin film transistor 4011included in the scan line driver circuit 4004. Over or below the thinfilm transistors 4010 and 4011, insulating layers 4041, 4042, 4020, and4021 are provided.

Any one of the thin film transistors described in Embodiments 2 to 9 canbe used as each of the thin film transistors 4010 and 4011 asappropriate, and can be formed using a similar process and a similarmaterial. In the oxide semiconductor layer of each of the thin filmtransistors 4010 and 4011, hydrogen or water is reduced. Thus, the thinfilm transistors 4010 and 4011 have high reliability. In thisembodiment, the thin film transistors 4010 and 4011 are n-channel thinfilm transistors.

A conductive layer 4040 is provided over part of the insulating layer4021, which overlaps with a channel formation region of the oxidesemiconductor layer in the thin film transistor 4011 for the drivecircuit. The conductive layer 4040 is provided at the positionoverlapping with the channel formation region of the oxide semiconductorlayer, whereby the amount of change in threshold voltage of the thinfilm transistor 4011 before and after a BT test can be reduced. Apotential of the conductive layer 4040 may be the same as or differentfrom that of a gate electrode layer of the thin film transistor 4011.The conductive layer 4040 can also function as a second gate electrodelayer. In addition, the potential of the conductive layer 4040 may beGND or 0 V, or the conductive layer 4040 may be in a floating state.

A pixel electrode layer 4030 included in the liquid crystal element 4013is electrically connected to a source electrode layer or a drainelectrode layer of the thin film transistor 4010. A counter electrodelayer 4031 of the liquid crystal element 4013 is provided on the secondsubstrate 4006. A portion where the pixel electrode layer 4030, thecounter electrode layer 4031, and the liquid crystal layer 4008 overlapwith each other corresponds to the liquid crystal element 4013. Notethat the pixel electrode layer 4030 and the counter electrode layer 4031are provided with an insulating layer 4032 and an insulating layer 4033respectively which each function as an alignment film, and the liquidcrystal layer 4008 is sandwiched between the pixel electrode layer 4030and the counter electrode layer 4031 with the insulating layers 4032 and4033 interposed therebetween.

Note that the first substrate 4001 and the second substrate 4006 can belight transmitting substrates and can be formed of glass, ceramic, orplastic. As plastic, a fiberglass-reinforced plastic (FRP) plate, apolyvinyl fluoride (PVF) film, a polyester film, or an acrylic resinfilm can be used.

A spacer 4035 is a columnar spacer obtained by selective etching of aninsulating film and is provided in order to control the distance (a cellgap) between the pixel electrode layer 4030 and the counter electrodelayer 4031. Alternatively, a spherical spacer may be used. In addition,the counter electrode layer 4031 is electrically connected to a commonpotential line formed over the same substrate as the thin filmtransistor 4010. With the use of a common connection portion, thecounter electrode layer 4031 and the common potential line can beelectrically connected to each other by conductive particles arrangedbetween a pair of substrates. Note that the conductive particles areincluded in the sealant 4005.

In addition, liquid crystal exhibiting a blue phase for which analignment film is unnecessary may be used. A blue phase is one of liquidcrystal phases, which is generated just before a cholesteric phasechanges into an isotropic phase while temperature of cholesteric liquidcrystal is increased. Since the blue phase is only generated within anarrow range of temperatures, a liquid crystal composition containing achiral agent at greater than or equal to 5 wt % is used for the liquidcrystal layer 4008 in order to widen the temperature range. The liquidcrystal composition which includes a liquid crystal exhibiting a bluephase and a chiral agent has a short response time of less than or equalto 1 msec, has optical isotropy, which makes the alignment processunneeded, and has a small viewing angle dependence. An alignment filmdoes not need to be provided and rubbing treatment is thus notnecessary; accordingly, electrostatic discharge damage caused by therubbing treatment can be prevented and defects and damage of the liquidcrystal display device in the manufacturing process can be reduced.Thus, productivity of the liquid crystal display device can be improved.A thin film transistor including an oxide semiconductor layerparticularly has a possibility that electrical characteristics of thethin film transistor may significantly change and deviate from thedesigned range by the influence of static electricity. Therefore, it ismore effective to use a blue phase liquid crystal material for a liquidcrystal display device having a thin film transistor including an oxidesemiconductor layer.

Note that the liquid crystal display device described in this embodimentis an example of a transmissive liquid crystal display device; however,an embodiment of the present invention can also be applied to either asemi-transmissive (transflective) or reflective liquid crystal displaydevice.

An example of the liquid crystal display device is illustrated in whicha polarizing plate is provided on the outer surface of the substrate (onthe viewer side) and a coloring layer and an electrode layer used for adisplay element are provided on the inner surface of the substrate inthis order; however, the polarizing plate may be provided on the innersurface of the substrate. The layered structure of the polarizing plateand the coloring layer is not limited to that described in thisembodiment and may be set as appropriate depending on materials of thepolarizing plate and the coloring layer or conditions of themanufacturing process. Further, a light blocking film serving as a blackmatrix may be provided in a region other than a display portion.

Over the thin film transistors 4011 and 4010, the insulating layer 4041is formed in contact with the oxide semiconductor layers. Here, as theinsulating layer 4041, a silicon oxide layer is formed by a sputteringmethod. Further, the protective insulating layer 4042 is formed on andin contact with the insulating layer 4041. For the protective insulatinglayer 4042, a silicon nitride film can be used, for example. Inaddition, in order to reduce the surface roughness of the thin filmtransistors, the protective insulating layer 4042 is covered with theinsulating layer 4021 functioning as a planarization insulating film.

The insulating layer 4021 is formed as the planarization insulatingfilm. As the insulating layer 4021, an organic material having heatresistance such as polyimide, acrylic, benzocyclobutene, polyamide, orepoxy can be used. Other than such organic materials, it is alsopossible to use a low-dielectric constant material (a low-k material), asiloxane-based resin, phosphosilicate glass (PSG), borophosphosilicateglass (BPSG), or the like. Note that the insulating layer 4021 may beformed by stacking a plurality of insulating films formed of thesematerials.

There is no particular limitation on the method for forming theinsulating layer 4021. The insulating layer 4021 can be formed,depending on the material, by a method such as a sputtering method, anSOG method, a spin coating method, a dipping method, a spray coatingmethod, or a droplet discharge method (e.g., an inkjet method, screenprinting, or offset printing), or a tool (equipment) such as a doctorknife, a roll coater, a curtain coater, or a knife coater. The bakingstep of the insulating layer 4021 also serves as annealing of thesemiconductor layer, whereby a liquid crystal display device can bemanufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 canbe formed using a light transmitting conductive material, such as indiumtin oxide (ITO), indium zinc oxide (IZO) in which zinc oxide (ZnO) ismixed in indium oxide, a conductive material in which silicon oxide(SiO₂) is mixed in indium oxide, organoindium, organotin, indium oxidecontaining tungsten oxide, indium zinc oxide containing tungsten oxide,indium oxide containing titanium oxide, or indium tin oxide containingtitanium oxide. Alternatively, in the case where a light transmittingproperty is not needed or a reflective property is needed for the pixelelectrode layer 4030 or the counter electrode layer 4031 in a reflectiveliquid crystal display device, the pixel electrode layer 4030 or thecounter electrode layer 4031 can be formed using one kind or pluralkinds selected from metal such as tungsten (W), molybdenum (Mo),zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta),chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt),aluminum (Al), copper (Cu), or silver (Ag), an alloy thereof, and anitride thereof.

A conductive composition containing a conductive high molecule (alsoreferred to as a conductive polymer) can be used for the pixel electrodelayer 4030 and the counter electrode layer 4031. The pixel electrodeformed using the conductive composition preferably has a sheetresistance of 10000 ohms per square or less and a transmittance of 70%or more at a wavelength of 550 nm. Further, the resistivity of theconductive high molecule contained in the conductive composition ispreferably 0.1 Ω·cm or less.

As the conductive high molecule, a so-called π-electron conjugatedconductive polymer can be used. For example, polyaniline or a derivativethereof, polypyrrole or a derivative thereof, polythiophene or aderivative thereof, a copolymer of two or more kinds of them, and thelike can be given.

Furthermore, a variety of signals and potentials are supplied to thesignal line driver circuit 4003 which is formed separately, the scanline driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

A connection terminal electrode 4015 is formed from the same conductivefilm as the pixel electrode layer 4030 included in the liquid crystalelement 4013, and a terminal electrode 4016 is formed from the sameconductive film as the source and drain electrode layers of the thinfilm transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to aterminal included in the FPC 4018 via an anisotropic conductive film4019.

FIGS. 15A to 15C illustrate an example in which the signal line drivercircuit 4003 is formed separately and mounted on the first substrate4001; however, this embodiment is not limited to this structure. Thescan line driver circuit may be separately formed and then mounted, oronly part of the signal line driver circuit or part of the scan linedriver circuit may be separately formed and then mounted.

A black matrix (a light blocking layer), an optical member (an opticalsubstrate) such as a polarizing member, a retardation member, or ananti-reflection member, and the like are provided as appropriate. Forexample, circular polarization may be employed by using a polarizingsubstrate and a retardation substrate. In addition, a backlight, asidelight, or the like may be used as a light source.

In an active matrix liquid crystal display device, display patterns areformed on a screen by driving of pixel electrodes that are arranged inmatrix. Specifically, voltage is applied between a selected pixelelectrode and a counter electrode corresponding to the pixel electrode,and thus, a liquid crystal layer disposed between the pixel electrodeand the counter electrode is optically modulated. This opticalmodulation is recognized as a display pattern by a viewer.

Since the thin film transistor is easily damaged due to staticelectricity or the like, a protective circuit is preferably providedover the same substrate as the pixel portion or the driver circuitportion. The protective circuit is preferably formed with a non-linearelement including an oxide semiconductor layer. For example, aprotective circuit is provided between the pixel portion, and a scanline input terminal and a signal line input terminal. In thisembodiment, a plurality of protective circuits is provided so that thepixel transistor and the like are not damaged when surge voltage due tostatic electricity or the like is applied to the scan line, the signalline, or a capacitor bus line. Accordingly, the protective circuit isconfigured to release charges to a common wiring when surge voltage isapplied to the protective circuit. The protective circuit includesnon-linear elements which are arranged in parallel between the scanline, the signal line, or the capacitor bus and the common wiring. Eachof the non-linear elements includes a two-terminal element such as adiode or a three-terminal element such as a transistor. For example, thenon-linear element can be formed through the same steps as the thin filmtransistor of the pixel portion. For example, characteristics similar tothose of a diode can be achieved by connecting a gate terminal to adrain terminal.

Further, for a liquid crystal display module, a twisted nematic (TN)mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS)mode, an axially symmetric aligned micro-cell (ASM) mode, an opticalcompensated birefringence (OCB) mode, a ferroelectric liquid crystal(FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the likecan be used.

There is no particular limitation on the kind of liquid crystal elementin the liquid crystal display device disclosed in this specification,and a transmissive liquid crystal display device including a TN liquidcrystal, an OCB liquid crystal, an STN liquid crystal, a VA liquidcrystal, an ECB liquid crystal, a GH liquid crystal, a polymer dispersedliquid crystal, a discotic liquid crystal, or the like can be used. Inparticular, a normally black liquid crystal panel such as a transmissiveliquid crystal display device utilizing a vertical alignment (VA) modeis preferable. These liquid crystal materials exhibit a cholestericphase, a smectic phase, a cubic phase, a chiral nematic phase, anisotropic phase, or the like depending on conditions. Some examples aregiven as a vertical alignment mode. For example, a multi-domain verticalalignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASVmode, or the like can be employed.

Furthermore, this embodiment can be applied to a VA liquid crystaldisplay device. The VA liquid crystal display device has a kind of formin which alignment of liquid crystal molecules of a liquid crystaldisplay panel is controlled. In the VA liquid crystal display device,liquid crystal molecules are aligned in a direction perpendicular to apanel surface when no voltage is applied. Moreover, it is possible touse a method called domain multiplication or multi-domain design, inwhich a pixel is divided into some regions (subpixels) and molecules arealigned in different directions in their respective regions.

Note that an embodiment of the present invention is not limited to aliquid crystal display device and can also be applied to a pixel of anEL display device which includes a light emitting element such as anelectroluminescent element (also referred to as an EL element) as adisplay element.

This embodiment can be implemented in appropriate combination with anyof other embodiments.

Embodiment 12

In this embodiment, examples of electronic devices including any of theliquid crystal display devices of the embodiments described above aredescribed.

FIG. 16A illustrates a portable game machine, which can include ahousing 9630, a display portion 9631, a speaker 9633, operation keys9635, a connection terminal 9636, a recording medium reading portion9672, and the like. The portable game machine illustrated in FIG. 16Acan have a function of reading a program or data stored in a recordingmedium to display it on the display portion, a function of sharinginformation with another portable game machine by wirelesscommunication, and the like. Note that the portable game machineillustrated in FIG. 16A can have various functions besides those givenabove.

FIG. 16B illustrates a digital camera, which can include the housing9630, the display portion 9631, the speaker 9633, the operation keys9635, the connection terminal 9636, a shutter button 9676, an imagereceiving portion 9677, and the like. The digital camera having atelevision reception function in FIG. 16B can have a function ofphotographing a still image and/or a moving image, a function ofautomatically or manually correcting the photographed image, a functionof obtaining various kinds of information from an antenna, a function ofstoring the photographed image or the information obtained from theantenna, and a function of displaying the photographed image or theinformation obtained from the antenna on the display portion. Note thatthe digital camera having the television reception function in FIG. 16Bcan have various functions besides those given above.

FIG. 16C illustrates a television set, which can include the housing9630, the display portion 9631, the speaker 9633, the operation keys9635, the connection terminal 9636, and the like. The television set inFIG. 16C can have a function of processing and converting an electricwave for television into an image signal, a function of processing andconverting the image signal into a signal suitable for display, afunction of converting a frame frequency of the image signal, and thelike. Note that the television set in FIG. 16C can have variousfunctions besides those given above.

FIG. 17A illustrates a computer, which can include the housing 9630, thedisplay portion 9631, the speaker 9633, the operation keys 9635, theconnection terminal 9636, a pointing device 9681, an external connectionport 9680, and the like. The computer in FIG. 17A can have a function ofdisplaying a variety of information (e.g., a still image, a movingimage, and a text image) on the display portion, a function ofcontrolling processing by a variety of software (programs), acommunication function such as wireless communication or wiredcommunication, a function of being connected to various computernetworks with the communication function, a function of transmitting orreceiving a variety of data with the communication function, and thelike. Note that the computer illustrated in FIG. 17A can have variousfunctions besides those given above.

FIG. 17B illustrates a mobile phone, which can include the housing 9630,the display portion 9631, the speaker 9633, the operation keys 9635, amicrophone 9638, and the like. The mobile phone in FIG. 17B can have afunction of displaying a variety of information (e.g., a still image, amoving image, and a text image) on the display portion, a function ofdisplaying a calendar, a date, the time, or the like on the displayportion, a function of operating or editing the information displayed onthe display portion, a function of controlling processing by variouskinds of software (programs), and the like. Note that the mobile phonein FIG. 17B can have various functions besides those given above.

FIG. 17C illustrates electronic paper (also referred to as an e-book),which can include the housing 9630, the display portion 9631, theoperation key 9635, and the like. The electronic paper in FIG. 17C canhave a function of displaying a variety of information (e.g., a stillimage, a moving image, and a text image) on the display portion, afunction of displaying a calendar, a date, the time, and the like on thedisplay portion, a function of operating or editing the informationdisplayed on the display portion, a function of controlling processingby various kinds of software (programs), and the like. Note that theelectronic paper in FIG. 17C can have various functions besides thosegiven above.

In each of the electronic devices described in this embodiment,off-state current can be decreased in a plurality of pixels included inthe display portion. Accordingly, an electronic device including aliquid crystal display device capable of extending the period in which astorage capacitor can hold a voltage and reducing power consumption whendisplaying a still image or the like can be obtained. Furthermore, by anincrease in aperture ratio, a liquid crystal display device having ahigh-definition display portion can be obtained.

This embodiment can be implemented in appropriate combination with anyof the structures described in other embodiments.

Embodiment 13

In this embodiment, a principle of operation of a bottom-gate transistorincluding an oxide semiconductor will be described.

FIG. 18 is a cross-sectional view of an inverted-staggeredinsulated-gate transistor including an oxide semiconductor. An oxidesemiconductor layer (OS) is provided over a gate electrode (GE1) with agate insulating film (GI) interposed therebetween, and a sourceelectrode (S) and a drain electrode (D) are provided thereover.

FIGS. 19A and 19B are energy band diagrams (schematic diagrams) along anA-A′ section illustrated in FIG. 18. FIG. 19A illustrates the case wherethe potential of a voltage applied to the source is equal to thepotential of a voltage applied to the drain (VD=0 V), and FIG. 19Billustrates the case where a positive potential with respect to thesource is applied to the drain (VD>0).

FIGS. 20A and 20B are energy band diagrams (schematic diagrams) along aB-B′ section illustrated in FIG. 18. FIG. 20A illustrates an on state inwhich a positive potential (+VG) is applied to the gate (G1) andcarriers (electrons) flow between the source and the drain. FIG. 20Billustrates an off state in which a negative potential (−VG) is appliedto the gate (G1) and minority carriers do not flow.

FIG. 21 illustrates the relationships between the vacuum level and thework function of a metal (φM) and between the vacuum level and theelectron affinity (χ) of an oxide semiconductor.

Because metal is degenerated, the conduction band and the Fermi levelcorrespond to each other. On the other hand, a conventional oxidesemiconductor is typically an n-type semiconductor, in which case theFermi level (Ef) is away from the intrinsic Fermi level (Ei) located inthe middle of a band gap and is located closer to the conduction band.Note that it is known that hydrogen is a donor in an oxide semiconductorand is one factor causing an oxide semiconductor to be an n-typesemiconductor.

On the other hand, an oxide semiconductor of the present invention is anintrinsic (i-type) or a substantially intrinsic oxide semiconductorwhich is obtained by removing hydrogen that is an n-type impurity froman oxide semiconductor and purifying the oxide semiconductor such thatan impurity other than a main component of the oxide semiconductor isprevented from being contained therein as much as possible. In otherwords, a feature is that a purified i-type (intrinsic) semiconductor, ora semiconductor close thereto, is obtained not by adding an impurity butby removing an impurity such as hydrogen or water as much as possible.This enables the Fermi level (Ef) to be at the same level as theintrinsic Fermi level (Ei).

In the case where the band gap (Eg) of an oxide semiconductor is 3.15eV, the electron affinity (χ) is said to be 4.3 eV. The work function oftitanium (Ti) included in the source electrode and the drain electrodeis substantially equal to the electron affinity (χ) of the oxidesemiconductor. In that case, a Schottky barrier for electrons is notformed at an interface between the metal and the oxide semiconductor.

In other words, in the case where the work function of metal (φM) andthe electron affinity (χ) of the oxide semiconductor are equal to eachother and the metal and the oxide semiconductor are in contact with eachother, an energy band diagram (a schematic diagram) as illustrated inFIG. 19A is obtained.

In FIG. 19B, a black circle () represents an electron, and when apositive potential is applied to the drain, the electron is injectedinto the oxide semiconductor over the barrier (h) and flows toward thedrain. In that case, the height of the barrier (h) changes depending onthe gate voltage and the drain voltage; in the case where a positivedrain voltage is applied, the height of the barrier (h) is smaller thanthe height of the barrier in FIG. 19A where no voltage is applied, i.e.,½ of the band gap (Eg).

The electron injected into the oxide semiconductor at this time flows inthe oxide semiconductor as illustrated in FIG. 20A. In addition, in FIG.20B, when a negative potential (reverse bias) is applied to the gateelectrode (G1), the value of current is extremely close to zero becauseholes that are minority carriers are substantially zero.

For example, even when an insulated-gate transistor as described abovehas a channel width W of 1×10⁴ μm and a channel length of 3 μm, theoff-state current is 10⁻¹³ A or less and the subthreshold swing (Svalue) is 0.1 V/dec (the thickness of the gate insulating film: 100 nm).

Note that the intrinsic carrier concentration of a silicon semiconductoris 1.45×10¹⁰/cm³ (300 K) and carriers exist even at room temperature.This means that thermally excited carriers exist even at roomtemperature. A silicon wafer to which an impurity such as phosphorus orboron is added is practically used. In addition, even in a so-calledintrinsic silicon wafer, impurities that cannot be controlled exist.Therefore, carriers exist in practice in a silicon semiconductor at1×10¹⁴/cm³ or more, which contributes to a conduction between the sourceand the drain. Furthermore, the band gap of a silicon semiconductor is1.12 eV, and thus the off-state current of a transistor including asilicon semiconductor significantly changes depending on temperature.

Therefore, not by simply using an oxide semiconductor having a wide bandgap for a transistor but by purifying the oxide semiconductor such thatan impurity other than a main component can be prevented from beingcontained therein as much as possible so that the carrier concentrationbecomes less than 1×10¹⁴/cm³, preferably 1×10¹²/cm³ or less, carriers tobe thermally excited at a practical operation temperature can beeliminated, and the transistor can be operated only with carriers thatare injected from the source side. This makes it possible to decreasethe off-state current to 1×10⁻¹³ A or less and to obtain a transistorwhose off-state current hardly changes with a change in temperature andwhich is capable of extremely stable operation.

A technical idea of the present invention is that an impurity is notadded to an oxide semiconductor and on the contrary the oxidesemiconductor itself is purified by removing an impurity such as wateror hydrogen which undesirably exists therein. In other words, a featureof an embodiment of the present invention is that an oxide semiconductoritself is purified by removing water or hydrogen which forms a donorlevel and further by sufficiently supplying oxygen to eliminate oxygendefects.

In an oxide semiconductor, even shortly after the deposition, hydrogenis observed on the order of 10²⁰/cm³ by secondary ion mass spectrometry(SIMS). One technical idea of the present invention is to purify anoxide semiconductor and obtain an electrically i-type (intrinsic)semiconductor by intentionally removing an impurity such as water orhydrogen which forms a donor level and further by adding oxygen (one ofcomponents of the oxide semiconductor), which decreases at the same timeas removing water or hydrogen, to the oxide semiconductor.

As a result, it is preferable that the amount of hydrogen be as small aspossible, and it is also preferable that the number of carriers in theoxide semiconductor be as small as possible. The oxide semiconductor isa purified i-type (intrinsic) semiconductor from which carriers havebeen eliminated and to which a meaning as a path of carriers as asemiconductor is given, rather than intentionally including carriers asa semiconductor, when used for an insulated-gate transistor.

As a result, by completely eliminating carriers from an oxidesemiconductor or significantly reducing carries therein, the off-statecurrent of an insulated-gate transistor can be decreased, which is atechnical idea of an embodiment of the present invention. In otherwords, as a criterion, the hydrogen concentration should be 1×10¹⁶/cm³or less and the carrier concentration should be less than 1×10¹⁴/cm³,preferably 1×10¹²/cm³ or less. According to a technical idea of thepresent invention, the ideal hydrogen concentration and carrierconcentration are zero or close to zero.

In addition, as a result, the oxide semiconductor functions as a path,and the oxide semiconductor itself is an i-type (intrinsic)semiconductor which is purified so as to include no carriers orextremely few carriers, and carriers are supplied by an electrode on thesource side. The degree of supply is determined by the barrier heightthat is obtained from the electron affinity χ of the oxidesemiconductor, the Fermi level, which ideally corresponds to theintrinsic Fermi level, and the work function of the source or drainelectrode.

Therefore, it is preferable that off-state current be as small aspossible, and a feature of an embodiment of the present invention isthat as characteristics of an insulated-gate transistor having a channellength of 10 μm, to which a drain voltage of 1 V to 10 V is applied, theoff-state current per micrometer of channel width is 10 aA/μm (1×10⁻¹⁷A/μm) or less, furthermore, 1 aA/μm (1×10⁻¹⁸ A/μm) or less.

Embodiment 14

In this embodiment, measured values of off-state current using a testelement group (also referred to as a TEG) will be described below.

FIG. 22 shows initial characteristics of a thin film transistor withL/W=3 μm/10000 μm in which 200 thin film transistors each with L/W=3μm/50 μm are connected in parallel. In addition, a top view is shown inFIG. 23A and a partially enlarged top view thereof is show in FIG. 23B.The region enclosed by a dotted line in FIG. 23B is a thin filmtransistor of one stage with L/W=3 μm/50 μm and Lov=1.5 μm. In order tomeasure initial characteristics of the thin film transistor, thechanging characteristics of the source-drain current (hereinafterreferred to as a drain current or Id), i.e., Vg-Id characteristics, weremeasured, under the conditions where the substrate temperature was setto room temperature, the voltage between source and drain (hereinafter,a drain voltage or Vd) was set to 10 V, and the voltage between sourceand gate (hereinafter, a gate voltage or Vg) was changed from −20 V to+20 V. Note that FIG. 22 shows Vg in the range of from −20 V to +5 V.

As shown in FIG. 22, the thin film transistor having a channel width Wof 10000 μm has an off-state current of 1×10⁻¹³ A or less at Vd of 1 Vand 10 V, which is less than or equal to the resolution (100 fA) of ameasurement device (a semiconductor parameter analyzer, Agilent 4156Cmanufactured by Agilent Technologies Inc.).

A method for manufacturing the thin film transistor used for themeasurement is described.

First, a silicon nitride layer was formed as a base layer over a glasssubstrate by a CVD method, and a silicon oxynitride layer was formedover the silicon nitride layer. A tungsten layer was formed as a gateelectrode layer over the silicon oxynitride layer by a sputteringmethod. Here, the gate electrode layer was formed by selectively etchingthe tungsten layer.

Then, a silicon oxynitride layer having a thickness of 100 nm was formedas a gate insulating layer over the gate electrode layer by a CVDmethod.

Then, an oxide semiconductor layer having a thickness of 50 nm wasformed over the gate insulating layer by a sputtering method using anIn—Ga—Zn—O-based oxide semiconductor target (at a molar ratio ofIn₂O₃:Ga₂O₃:ZnO=1:1:2). Here, an island-shaped oxide semiconductor layerwas formed by selectively etching the oxide semiconductor layer.

Then, first heat treatment was performed on the oxide semiconductorlayer in a nitrogen atmosphere in a clean oven at 450° C. for 1 hour.

Then, a titanium layer (having a thickness of 150 nm) was formed as asource electrode layer and a drain electrode layer over the oxidesemiconductor layer by a sputtering method. Here, the source electrodelayer and the drain electrode layer were formed by selective etchingsuch that 200 thin film transistors each having a channel length L of 3μm and a channel width W of 50 μm were connected in parallel to obtain athin film transistor with L/W=3 μm/10000 μm.

Then, a silicon oxide layer having a thickness of 300 nm was formed as aprotective insulating layer in contact with the oxide semiconductorlayer by a reactive sputtering method. Here, opening portions wereformed over the gate electrode layer, the source electrode layer, andthe drain electrode layer by selectively etching the silicon oxide layerwhich is a protective layer. After that, second heat treatment wasperformed in a nitrogen atmosphere at 250° C. for 1 hour.

Then, heat treatment was performed at 150° C. for 10 hours before themeasurement of Vg-Id characteristics.

Through the above process, a bottom-gate thin film transistor wasmanufactured.

The reason why the thin film transistor has an off-state current ofapproximately 1×10⁻¹³ A as shown in FIG. 22 is that the concentration ofhydrogen in the oxide semiconductor layer could be sufficiently reducedin the above manufacturing process. The concentration of hydrogen in theoxide semiconductor layer is 1×10¹⁶/cm³ or less. Note that theconcentration of hydrogen in the oxide semiconductor layer was measuredby secondary ion mass spectrometry (SIMS).

Although the example of using an In—Ga—Zn—O-based oxide semiconductor isdescribed, this embodiment is not particularly limited thereto. Anotheroxide semiconductor material, such as an In—Sn—Zn—O-based oxidesemiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, anAl—Ga—Zn—O-based oxide semiconductor, a Sn—Al—Zn—O-based oxidesemiconductor, an In—Zn—O-based oxide semiconductor, an In—Sn—O-basedoxide semiconductor, a Sn—Zn—O-based oxide semiconductor, anAl—Zn—O-based oxide semiconductor, an In—O-based oxide semiconductor, aSn—O-based oxide semiconductor, or a Zn—O-based oxide semiconductor, canalso be used. Furthermore, as an oxide semiconductor material, anIn—Al—Zn—O-based oxide semiconductor mixed with AlO_(x) of 2.5 wt % to10 wt % or an In—Zn—O-based oxide semiconductor mixed with SiO_(x) of2.5 wt % to 10 wt % can be used.

The carrier concentration of the oxide semiconductor layer which ismeasured by a carrier measurement device is less than 1×10¹⁴/cm³,preferably 1×10¹²/cm³ or less. In other words, the carrier concentrationof the oxide semiconductor layer can be made as close to zero aspossible.

The thin film transistor can also have a channel length L of 10 nm to1000 nm, which enables an increase in circuit operation speed, and theoff-state current is extremely small, which enables a further reductionin power consumption.

In addition, in circuit design, the oxide semiconductor layer can beregarded as an insulator when the thin film transistor is in an offstate.

After that, the temperature characteristics of off-state current of thethin film transistor manufactured in this embodiment were evaluated.Temperature characteristics are important in considering theenvironmental resistance, maintenance of performance, or the like of anend product in which the thin film transistor is used. It is to beunderstood that a smaller amount of change is more preferable, whichincreases the degree of freedom for product designing.

For the temperature characteristics, the Vg-Id characteristics wereobtained using a constant-temperature chamber under the conditions wheresubstrates provided with thin film transistors were kept at respectiveconstant temperatures of −30° C., 0° C., 25° C., 40° C., 60° C., 80° C.,100° C., and 120° C., the drain voltage was set to 6 V, and the gatevoltage was changed from −20 V to +20V.

FIG. 24A shows Vg-Id characteristics measured at the above temperaturesand superimposed on one another, and FIG. 24B shows an enlarged view ofa range of off-state current enclosed by a dotted line in FIG. 24A. Therightmost curve indicated by an arrow in the diagram is a curve obtainedat −30° C.; the leftmost curve is a curve obtained at 120° C.; andcurves obtained at the other temperatures are located therebetween. Thetemperature dependence of on-state currents can hardly be observed. Onthe other hand, as clearly shown also in the enlarged view of FIG. 24B,the off-state currents are less than or equal to 1×10⁻¹² A, which isnear the resolution of the measurement device, at all temperaturesexcept in the vicinity of a gate voltage of −20 V, and the temperaturedependence thereof is not observed. In other words, even at a hightemperature of 120° C., the off-state current is kept less than or equalto 1×10⁻¹² A, and given that the channel width W is 10000 μm, it can beseen that the off-state current is significantly small.

A thin film transistor including a purified oxide semiconductor(purified OS) as described above shows almost no dependence of off-statecurrent on temperature. It can be said that an oxide semiconductor doesnot show temperature dependence when purified because the conductivitytype becomes extremely close to an intrinsic type and the Fermi level islocated in the middle of the forbidden band, as illustrated in the banddiagram of FIG. 20A. This also results from the fact that the oxidesemiconductor has an energy gap of 3 eV or more and includes very fewthermally excited carriers. In addition, the source region and the drainregion are in a degenerated state, which is also a factor for showing notemperature dependence. The thin film transistor is mainly operated withcarriers which are injected from the degenerated source region to theoxide semiconductor, and the above characteristics (independence ofoff-state current on temperature) can be explained by independence ofcarrier concentration on temperature.

In the case where a display device or the like is manufactured using athin film transistor having such an extremely small off-state current,there is very little leakage. Therefore, display data can be held for alonger period of time.

Embodiment 15

In this embodiment, an example of a structure of a shift registerincluded in each of a scan line driver circuit and a signal line drivercircuit of a liquid crystal display device which is one embodiment ofthe present invention is described using FIGS. 25A to 25C.

The shift register shown in FIG. 25A includes first to N-th pulse outputcircuits 10_1 to 10_N (N is a natural number of 3 or more). A firstclock signal CK1 from a first wiring 11, a second clock signal CK2 froma second wiring 12, a third clock signal CK3 from a third wiring 13, anda fourth clock signal CK4 from a fourth wiring 14 are supplied to thefirst to the N-th pulse output circuits 10_1 to 10_N of the shiftregister shown in FIG. 25A. A start pulse SP1 (a first start pulse) froma fifth wiring 15 is input to the first pulse output circuit 10_1. Asignal from the pulse output circuit in the previous stage (the signalcalled a previous stage signal OUT(n−1)) (n is a natural number of morethan or equal to 2 and lower than or equal to N) is input to the n-thpulse output circuit 10_N in the second or later stage. A signal fromthe third pulse output circuit 10_3 in the stage two stages after thefirst pulse output circuit 10_1 is input to the first pulse outputcircuit 10_1; similarly, a signal from the (n+2)-th pulse output circuit10(n+2) in the stage two stages after the n-th pulse output circuit 10_n(the signal called a subsequent-stage signal OUT(n+2)) is input to then-th pulse output circuit. In this manner, a first output signal(corresponding one of OUT(1)(SR) to OUT(N)(SR)) to be input to the pulseoutput circuit of the next stage and/or the two-stage-previous stage anda second output signal (corresponding one of OUT(1) to OUT(N)) which isinput to another circuit or the like are output from each of the pulseoutput circuits. Note that as shown in FIG. 25A, the subsequent-stagesignal OUT(n+2) is not input to the last two stages of the shiftregister; therefore, as an example, a second start pulse SP2 may beinput to one of the last two stages of the shift register and a thirdstart pulse SP3 may be input to the other of the same. Alternatively,signals may be generated inside the shift register. For example, a(N+1)-th pulse output circuit 10 _((N+1)) and a (N+2)-th pulse outputcircuit 10 _((N+2)) which do not contribute to output of pulses to thepixel portion (such circuits are also referred to as dummy stages) maybe provided, and signals corresponding to the second start pulse (SP2)and the third start pulse (SP3) may be generated in the dummy stages.

Note that the first to the fourth clock signals (CK1) to (CK4) each area signal which oscillates between an H-level signal and an L-levelsignal at a constant cycle. The first to the fourth clock signals (CK1)to (CK4) are delayed by ¼ period sequentially. In this embodiment, byusing the first to fourth clock signals (CK1) to (CK4), control ofdriving of the pulse output circuit or the like is performed. Note thatthe clock signal CK is also called GCK or SCK depending on a drivercircuit to which the clock signal is input; however, description is madein this embodiment by using CK as the clock signal.

Note that when it is explicitly described that “A and B are connected,”the case where A and B are electrically connected, the case where A andB are functionally connected, and the case where A and B are directlyconnected are included therein. Here, each of A and B corresponds to anobject (e.g., a device, an element, a circuit, a wiring, an electrode, aterminal, a conductive film, or a layer). Accordingly, other connectionrelations are included without being limited to a predeterminedconnection relation, for example, the connection relation shown in thedrawings and the texts.

Each of the first to N-th pulse output circuits 10_1 to 10_N includes afirst input terminal 21, a second input terminal 22, a third inputterminal 23, a fourth input terminal 24, a fifth input terminal 25, afirst output terminal 26, and a second output terminal 27 (see FIG.25B).

The first input terminal 21, the second input terminal 22, and the thirdinput terminal 23 are electrically connected to any of the first tofourth wirings 11 to 14. For example, in FIGS. 25A and 25B, the firstinput terminal 21 of the first pulse output circuit 10_1 is electricallyconnected to the first wiring 11, the second input terminal 22 of thefirst pulse output circuit 10_1 is electrically connected to the secondwiring 12, and the third input terminal 23 of the first pulse outputcircuit 10_1 is electrically connected to the third wiring 13. Inaddition, the first input terminal 21 of the second pulse output circuit102 is electrically connected to the second wiring 12, the second inputterminal 22 of the second pulse output circuit 102 is electricallyconnected to the third wiring 13, and the third input terminal 23 of thesecond pulse output circuit 10_2 is electrically connected to the fourthwiring 14.

In FIGS. 25A and 25B, in the first pulse output circuit 10_1, the firststart pulse SP1 is input to the fourth input terminal 24, asubsequent-stage signal OUT(3) is input to the fifth input terminal 25,the first output signal OUT(1)(SR) is output from the first outputterminal 26, and the second output signal OUT(1) is output from thesecond output terminal 27.

Next, an example of a specific circuit structure of the pulse outputcircuit is described with reference to FIG. 25C.

In FIG. 25C, a first terminal of the first transistor 31 is electricallyconnected to the power supply line 51, a second terminal of the firsttransistor 31 is electrically connected to a first terminal of the ninthtransistor 39, and a gate electrode of the first transistor 31 iselectrically connected to the fourth input terminal 24. A first terminalof the second transistor 32 is electrically connected to the powersupply line 52, a second terminal of the second transistor 32 iselectrically connected to the first terminal of the ninth transistor 39,and a gate electrode of the second transistor 32 is electricallyconnected to a gate electrode of the fourth transistor 34. A firstterminal of the third transistor 33 is electrically connected to thefirst input terminal 21, and a second terminal of the third transistor33 is electrically connected to the first output terminal 26. A firstterminal of the fourth transistor 34 is electrically connected to thepower supply line 52, and a second terminal of the fourth transistor 34is electrically connected to the first output terminal 26. A firstterminal of the fifth transistor 35 is electrically connected to thepower supply line 52, a second terminal of the fifth transistor 35 iselectrically connected to the gate electrode of the second transistor 32and the gate electrode of the fourth transistor 34, and a gate electrodeof the fifth transistor 35 is electrically connected to the fourth inputterminal 24. A first terminal of the sixth transistor 36 is electricallyconnected to the power supply line 51, a second terminal of the sixthtransistor 36 is electrically connected to the gate electrode of thesecond transistor 32 and the gate electrode of the fourth transistor 34,and a gate electrode of the sixth transistor 36 is electricallyconnected to the fifth input terminal 25. A first terminal of theseventh transistor 37 is electrically connected to the power supply line51, a second terminal of the seventh transistor 37 is electricallyconnected to a second terminal of the eighth transistor 38, and a gateelectrode of the seventh transistor 37 is electrically connected to thethird input terminal 23. A first terminal of the eighth transistor 38 iselectrically connected to the gate electrode of the second transistor 32and the gate electrode of the fourth transistor 34, and a gate electrodeof the eighth transistor 38 is electrically connected to the secondinput terminal 22. The first terminal of the ninth transistor 39 iselectrically connected to the second terminal of the first transistor 31and the second terminal of the second transistor 32, a second terminalof the ninth transistor 39 is electrically connected to the gateelectrode of the third transistor 33 and the gate electrode of the tenthtransistor 40, and a gate electrode of the ninth transistor 39 iselectrically connected to the power supply line 51. A first terminal ofthe tenth transistor 40 is electrically connected to the first inputterminal 21, a second terminal of the tenth transistor 40 iselectrically connected to the second output terminal 27, and the gateelectrode of the tenth transistor 40 is electrically connected to thesecond terminal of the ninth transistor 39. A first terminal of theeleventh transistor 41 is electrically connected to the power supplyline 52, a second terminal of the eleventh transistor 41 is electricallyconnected to the second output terminal 27, and a gate electrode of theeleventh transistor 41 is electrically connected to the gate electrodeof the second transistor 32 and the gate electrode of the fourthtransistor 34.

In FIG. 25C, a connection point of the gate electrode of the thirdtransistor 33, the gate electrode of the tenth transistor 40, and thesecond terminal of the ninth transistor 39 is referred to as a node NA.In addition, a connection point of the gate electrode of the secondtransistor 32, the gate electrode of the fourth transistor 34, thesecond terminal of the fifth transistor 35, the second terminal of thesixth transistor 36, the first terminal of the eighth transistor 38, andthe gate electrode of the eleventh transistor 41 is referred to as anode NB.

In the case where the pulse output circuit in FIG. 25C is the firstpulse output circuit 10_1, the first clock signal CK1 is input to thefirst input terminal 21, the second clock signal CK2 is input to thesecond input terminal 22, the third clock signal CK3 is input to thethird input terminal 23, the start pulse SP is input to the fourth inputterminal 24, a subsequent-stage signal OUT(3) is input to the fifthinput terminal 25, the first output signal OUT(1)(SR) is output from thefirst output terminal 26, and the second output signal OUT(1) is outputfrom the second output terminal 27.

FIG. 26 shows a timing chart of a shift register including the pluralityof pulse output circuits shown in FIG. 25C. In the case where the shiftregister is a scan line driver circuit, a period 61 in FIG. 26 is avertical retrace period and a period 62 is a gate selection period.

The procedure of supplying, or stopping the supply of, a potential toeach wiring of the driver circuit portion during the operations todisplay a still image and a moving image, or the operation to rewrite avoltage to be applied to a liquid crystal element (hereinafter alsoreferred to as refresh operation), in the driver circuit manufacturedusing a plurality of n-channel transistors, which is given as an examplein FIGS. 25A to 25C and FIG. 26, will be described with reference toFIG. 27. Note that FIG. 27 illustrates changes in potentials, before andafter a period T1, of a wiring for supplying a high power supplypotential (VDD), a wiring for supplying a low power supply potential(VSS), a wiring for supplying a start pulse (SP), and wirings forsupplying first to fourth clock signals (CK1 to CK4) to a shiftregister.

The liquid crystal display device of this embodiment can display a stillimage without constantly operating the driver circuit portion.Therefore, as illustrated in FIG. 27, there are a period in whichcontrol signals such as the high power supply potential (VDD), the firstto fourth clock signals (CK1 to CK4), and the start pulse are suppliedto a shift register and a period in which control signals are notsupplied. Note that the period T1 illustrated in FIG. 27 corresponds tothe period in which control signals are supplied, in other words, aperiod in which a moving image is displayed and a period in whichrefresh operation is performed. The period T2 illustrated in FIG. 27corresponds to the period in which control signals are not supplied, inother words, a period in which a still image is displayed.

In FIG. 27, a period in which the high power supply potential (VDD) issupplied is provided not only in the period T1 but also in part of theperiod T2. In addition, in FIG. 27, a period in which the first tofourth clock signals (CK1 to CK4) are supplied is provided between thestart of the supply of the high power supply potential (VDD) and thestop of the supply of the high power potential (VDD).

Moreover, as illustrated in FIG. 27, the first to fourth clock signals(CK1 to CK4) may be set so as to start to oscillate at a constantfrequency after being set to a high potential once before the period T1begins and stop oscillating after being set to a low potential after theperiod T1 ends.

As described above, in the liquid crystal display device of thisembodiment, the supply of control signals such as the high power supplypotential (VDD), the first to fourth clock signals (CK1 to CK4), and thestart pulse to the shift register is stopped in the period T2. Then, inthe period in which the supply of control signals is stopped, whethereach transistor is turned on or turned off is controlled and the outputof a pulse signal from the shift register is also stopped. Therefore,power consumption of the shift register and power consumption of thepixel portion which is driven by the shift register can be reduced.

Note that the aforementioned refresh operation needs to be performedregularly because there is a possibility that the quality of a displayedstill image may deteriorate. In the liquid crystal display device ofthis embodiment, the aforementioned transistor including an oxidesemiconductor is employed as a switching element for controlling avoltage to be applied to a liquid crystal element of each pixel.Accordingly, off-state current can be drastically decreased, and achange in voltage to be applied to the liquid crystal element of eachpixel can be reduced. In other words, even when the period in which theoperation of the shift register is stopped is long due to display of astill image, the deterioration of image quality can be suppressed. Forexample, even when the period is 3 minutes long, the quality of adisplayed still image can be maintained. For example, if a liquidcrystal display device in which rewrite is performed 60 times per secondand a liquid crystal display device in which refresh operation isperformed once in 3 minutes are compared with each other, powerconsumption can be reduced to approximately 1/10000.

Note that the stop of the supply of the high power supply potential(VDD) is to set a potential equal to the low power supply potential(VSS) as illustrated in FIG. 27. In addition, the stop of the supply ofthe high power supply potential (VDD) may be to set the potential of awiring, to which the high power supply potential is supplied, in afloating state.

Note that when the potential of the wiring to which the high powersupply potential (VDD) is supplied is increased, which means that thepotential is increased from the low power supply potential (VSS) to thehigh power supply potential (VDD) before the period T1, it is preferablethat the potential of the wiring is controlled so as to changegradually. If the gradient of the change in potential of the wiring issteep, there is a possibility that the change in potential may becomenoise and an irregular pulse may be output from the shift register. Inthe case where the shift register is included in a gate line drivercircuit, the irregular pulse serves as a signal for turning on atransistor. Thus, there is a possibility that a voltage to be applied toa liquid crystal element may be changed by the irregular pulse and thequality of a still image may be changed. Therefore, it is preferable tocontrol the change in potential of the wiring as described above. Inview of the above content, FIG. 27 illustrates an example in which arise in signal to the high power supply potential (VDD) is more gradualthan a fall. In particular, in the liquid crystal display device of thisembodiment, when a still image is displayed in the pixel portion, thestop of the supply, and the resupply, of the high power supply potential(VDD) to the shift register are performed as appropriate. In otherwords, in the case where a change in potential of the wiring forsupplying the high power supply potential (VDD) adversely affects thepixel portion as noise, the noise directly leads to deterioration of adisplay image. Therefore, it is important to control the liquid crystaldisplay device of this embodiment so as to prevent a change in potential(particularly, an increase in potential) of the wiring from entering thepixel portion as noise.

Furthermore, in this embodiment, when a still image is displayed, byoperating the driver circuit portion so as to stop the output of asignal to be supplied to a signal line or a scan line, power consumptionof the driver circuit portion as well as the pixel portion can bereduced.

Note that this embodiment can be combined with any of other embodimentsas appropriate.

Example 1

In this example, the results of evaluation of image signal holdingcharacteristics of the liquid crystal display device, which is describedin the above embodiment and actually manufactured, at the time ofdisplaying a still image will be described.

First, a photograph of a display state of the manufactured liquidcrystal display device is shown in FIG. 28. From the photograph of theliquid crystal display device of FIG. 28, a state of the actuallymanufactured liquid crystal display device displaying a still image canbe seen.

Next, regarding an upper-side layout diagram of a plurality of pixelsincluded in a pixel portion, a photograph of elements such as thin filmtransistors formed over a substrate, which is taken from the rear side,is shown in FIG. 29.

From the photograph of the pixels shown in FIG. 29, it can be seen thatrectangular pixels are provided and gate lines 2901 and signal lines2902 are provided at right angles to each other. It can also be seenthat capacitor lines 2903 are provided in a position parallel with thegate lines 2901. In a region where the gate line 2901 and the capacitorline 2903, and the signal line 2902 overlap each other, an insulatingfilm is provided in order to reduce parasitic capacitance, and can beobserved as a bump in FIG. 29. The liquid crystal display devicedescribed in this example is a reflective liquid crystal display device,and a reflective electrode 2904R overlapping a red (R) color filter, areflective electrode 2904G overlapping a green (G) color filter, and areflective electrode 2904B overlapping a blue (B) color filter areobserved. In FIG. 29, in a region controlled by the gate line 2901, anIn—Ga—Zn—O-based non-single-crystal film which is an oxide semiconductoris provided as a light transmitting semiconductor layer, and a thin filmtransistor is formed.

FIG. 30 shows a graph of changes in luminance over time of each pixelshown in FIG. 29 at the time of displaying a still image according tothe above embodiment.

It can be seen from FIG. 30 that in the case of the upper-side layout ofthe pixel of FIG. 29, the image signal holding period is approximately 1minute long. Therefore, at the time of displaying a still image, aconstant luminance may be maintained by performing the operation toregularly supply the same image signal (in the diagram, “refresh”). As aresult, the length of time to apply a voltage to a transistor includedin a driver circuit portion can be drastically shortened. Furthermore,deterioration of a driver circuit over time can be drastically slowed,which produces advantageous effects such as an improvement inreliability of a liquid crystal display device.

This application is based on Japanese Patent Application serial no.2009-238869 filed with Japan Patent Office on Oct. 16, 2009 and JapanesePatent Application serial no. 2009-279004 filed on Dec. 8, 2009, theentire contents of which are hereby incorporated by reference.

1. (canceled)
 2. A display device comprising: a transistor comprising asource, a drain and a channel formation region, the channel formationregion comprising an oxide semiconductor; a pixel electrode electricallyconnected to the source or the drain of the transistor; and a liquidcrystal material adjacent to the pixel electrode, wherein a specificresistance of the liquid crystal material measured at 20° C. is 1×10¹²Ω·cm or more.
 3. A display device comprising: a transistor comprising asource, a drain and a channel formation region, the channel formationregion comprising an oxide semiconductor; and a pixel electrodeelectrically connected to the source or the drain of the transistor,wherein an energy gap of the oxide semiconductor is 2 eV or more, andwherein a current per micrometer of a channel width of the channelformation region is 1×10⁻¹⁷ A or less.
 4. A display device comprising aplurality of pixels in a display portion and configured to performdisplay in a plurality of frame periods, each of the plurality of pixelscomprising: a transistor comprising a source, a drain and a channelformation region, the channel formation region comprising an oxidesemiconductor; and a pixel electrode electrically connected to thesource or the drain of the transistor, wherein each of the plurality offrame periods includes a writing period and a holding period, whereinthe holding period is variable, and wherein the pixel electrode is areflective electrode.
 5. A display device comprising a plurality ofpixels in a display portion and configured to perform display in aplurality of frame periods, each of the plurality of pixels comprising:a transistor comprising a source, a drain and a channel formationregion, the channel formation region comprising an oxide semiconductor;and a pixel electrode electrically connected to the source or the drainof the transistor, wherein each of the plurality of frame periodsincludes a writing period and a holding period, wherein the holdingperiod is within a range such that an image burn-in does not occur, andwherein the pixel electrode is a reflective electrode.
 6. A displaydevice comprising a plurality of pixels in a display portion andconfigured to perform display in a plurality of frame periods, each ofthe plurality of pixels comprising: a transistor comprising a source, adrain and a channel formation region, the channel formation regioncomprising an oxide semiconductor; and a pixel electrode electricallyconnected to the source or the drain of the transistor, wherein each ofthe plurality of frame periods includes a writing period and a holdingperiod, wherein the holding period is at least 10 seconds, and whereinthe pixel electrode is a reflective electrode.
 7. A display devicecomprising: a transistor comprising a source, a drain and a channelformation region, the channel formation region comprising an oxidesemiconductor; and a pixel electrode electrically connected to thesource or the drain of the transistor, wherein a frequency of signalwriting of a still image is lower than that of a moving image.
 8. Thedisplay device according to claim 2, wherein the oxide semiconductorincludes indium.
 9. The display device according to claim 3, wherein theoxide semiconductor includes indium.
 10. The display device according toclaim 4, wherein the oxide semiconductor includes indium.
 11. Thedisplay device according to claim 5, wherein the oxide semiconductorincludes indium.
 12. The display device according to claim 6, whereinthe oxide semiconductor includes indium.
 13. The display deviceaccording to claim 7, wherein the oxide semiconductor includes indium.14. The display device according to claim 2, wherein the oxidesemiconductor includes a microcrystalline portion with a grain diameterof 1 nm to 20 nm.
 15. The display device according to claim 3, whereinthe oxide semiconductor includes a microcrystalline portion with a graindiameter of 1 nm to 20 nm.
 16. The display device according to claim 4,wherein the oxide semiconductor includes a microcrystalline portion witha grain diameter of 1 nm to 20 nm.
 17. The display device according toclaim 5, wherein the oxide semiconductor includes a microcrystallineportion with a grain diameter of 1 nm to 20 nm.
 18. The display deviceaccording to claim 6, wherein the oxide semiconductor includes amicrocrystalline portion with a grain diameter of 1 nm to 20 nm.
 19. Thedisplay device according to claim 7, wherein the oxide semiconductorincludes a microcrystalline portion with a grain diameter of 1 nm to 20nm.
 20. The display device according to claim 3, wherein the displaydevice is a liquid crystal display device, an electroluminescent displaydevice, or a display device using electronic ink.
 21. The display deviceaccording to claim 4, wherein the display device is a liquid crystaldisplay device, an electroluminescent display device, or a displaydevice using electronic ink.
 22. The display device according to claim5, wherein the display device is a liquid crystal display device, anelectroluminescent display device, or a display device using electronicink.
 23. The display device according to claim 6, wherein the displaydevice is a liquid crystal display device, an electroluminescent displaydevice, or a display device using electronic ink.
 24. The display deviceaccording to claim 7, wherein the display device is a liquid crystaldisplay device, an electroluminescent display device, or a displaydevice using electronic ink.
 25. The display device according to claim2, wherein an energy gap of the oxide semiconductor is 2 eV or more, andwherein a current per micrometer of a channel width of the channelformation region is 1×10⁻¹⁷ A or less.
 26. The display device accordingto claim 4, wherein an energy gap of the oxide semiconductor is 2 eV ormore, and wherein a current per micrometer of a channel width of thechannel formation region is 1×10⁻¹⁷ A or less.
 27. The display deviceaccording to claim 5, wherein an energy gap of the oxide semiconductoris 2 eV or more, and wherein a current per micrometer of a channel widthof the channel formation region is 1×10⁻¹⁷ A or less.
 28. The displaydevice according to claim 6, wherein an energy gap of the oxidesemiconductor is 2 eV or more, and wherein a current per micrometer of achannel width of the channel formation region is 1×10⁻¹⁷ A or less. 29.The display device according to claim 7, wherein an energy gap of theoxide semiconductor is 2 eV or more, and wherein a current permicrometer of a channel width of the channel formation region is 1×10⁻¹⁷A or less.
 30. The display device according to claim 2, wherein thepixel electrode is a reflective electrode.
 31. The display deviceaccording to claim 3, wherein the pixel electrode is a reflectiveelectrode.
 32. The display device according to claim 7, wherein thepixel electrode is a reflective electrode.
 33. The display deviceaccording to claim 4, wherein the pixel electrode includes at least oneselected from a group consisting of tungsten, molybdenum, zirconium,hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel,titanium, platinum, aluminum, copper, and silver.
 34. The display deviceaccording to claim 5, wherein the pixel electrode includes at least oneselected from a group consisting of tungsten, molybdenum, zirconium,hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel,titanium, platinum, aluminum, copper, and silver.
 35. The display deviceaccording to claim 6, wherein the pixel electrode includes at least oneselected from a group consisting of tungsten, molybdenum, zirconium,hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel,titanium, platinum, aluminum, copper, and silver.
 36. The display deviceaccording to claim 3, further comprising a liquid crystal layer, whereinthe liquid crystal layer comprises a twisted nematic mode.
 37. Thedisplay device according to claim 6, further comprising a liquid crystallayer, wherein the liquid crystal layer comprises a twisted nematicmode.
 38. The display device according to claim 7, further comprising aliquid crystal layer, wherein the liquid crystal layer comprises atwisted nematic mode.
 39. The display device according to claim 3,wherein the oxide semiconductor has a carrier concentration of less than1×10¹⁴/cm³.
 40. The display device according to claim 4, wherein theholding period is variable in accordance with a holding rate of avoltage applied to a display element during the holding period.
 41. Thedisplay device according to claim 5, wherein a polarity of a voltageapplied to a display element is inverted in each of the plurality offrame periods.
 42. The display device according to claim 2, wherein thedisplay device is configured to perform display in a plurality of frameperiods, wherein each of the plurality of frame periods includes awriting period and a holding period, and wherein the holding period iswithin a range such that an image burn-in does not occur.
 43. Thedisplay device according to claim 3, wherein the display device isconfigured to perform display in a plurality of frame periods, whereineach of the plurality of frame periods includes a writing period and aholding period, and wherein the holding period is within a range suchthat an image burn-in does not occur.
 44. The display device accordingto claim 7, wherein the display device is configured to perform displayin a plurality of frame periods, wherein each of the plurality of frameperiods includes a writing period and a holding period, and wherein theholding period is within a range such that an image burn-in does notoccur.
 45. The display device according to claim 3, further comprising aliquid crystal material adjacent to the pixel electrode, wherein aspecific resistance of the liquid crystal material measured at 20° C. is1×10¹² Ω·cm or more.
 46. The display device according to claim 4,further comprising a liquid crystal material adjacent to the pixelelectrode, wherein a specific resistance of the liquid crystal materialmeasured at 20° C. is 1×10¹² Ω·cm or more.
 47. The display deviceaccording to claim 5, further comprising a liquid crystal materialadjacent to the pixel electrode, wherein a specific resistance of theliquid crystal material measured at 20° C. is 1×10¹² Ω·cm or more. 48.The display device according to claim 6, further comprising a liquidcrystal material adjacent to the pixel electrode, wherein a specificresistance of the liquid crystal material measured at 20° C. is 1×10¹²Ω·cm or more.
 49. The display device according to claim 7, furthercomprising a liquid crystal material adjacent to the pixel electrode,wherein a specific resistance of the liquid crystal material measured at20° C. is 1×10¹² Ω·cm or more.
 50. The display device according to claim2, wherein the specific resistance of the liquid crystal materialmeasured at 20° C. is 1×10¹⁴ Ω·cm or more.
 51. The display deviceaccording to claim 4, wherein a refresh operation is performed at atiming when a voltage applied to a display element is decreased to apredetermined level with respect to an initial value.
 52. The displaydevice according to claim 5, wherein the display device is driven by dotinversion driving.
 53. The display device according to claim 6, whereinthe display device is driven by dot inversion driving.
 54. The displaydevice according to claim 7, wherein the display device is driven by dotinversion driving.